source: mainline/boot/arch/ia64/src/sal_asm.S@ fb48a0e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since fb48a0e was 577fe9b6, checked in by Jakub Jermar <jakub@…>, 14 years ago

Support for calling SAL procedures from the loader.

  • Added sal_call() to perform and wrap around calls to SAL.
  • Added sal_base_clock_frequency() to read the system base frequency.
  • Property mode set to 100644
File size: 2.2 KB
RevLine 
[577fe9b6]1#
2# Copyright (c) 2011 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29.explicit
30
31.global sal_call
32
33#
34# Assume the following PSR bits are already 0, as expected by SAL:
35#
36# be, cpl, is, da, dd, ss, ri, ed, ia
37#
38# Assume PSR.bn is 1, as expected by SAL.
39#
40sal_call:
41 alloc loc0 = ar.pfs, 11, 5, 8, 0
42
43 mov loc1 = gp
44 mov loc2 = rp
45
46 addl loc3 = @gprel(sal_proc), gp
47 addl loc4 = @gprel(sal_proc_gp), gp
48
49 mov out0 = in0
50 mov out1 = in1
51 mov out2 = in2
52 mov out3 = in3
53 mov out4 = in4
54 mov out5 = in5
55 mov out6 = in6
56 mov out7 = in7 ;;
57
58 ld8 loc3 = [loc3]
59 ld8 gp = [loc4] ;;
60
61 mov b6 = loc3 ;;
62 br.call.sptk.many rp = b6
63
64 cmp.ne p7,p0 = 0, in8
65 cmp.ne p8,p0 = 0, in9
66 cmp.ne p9,p0 = 0, in10 ;;
67
68(p7) st8 [in8] = r9
69(p8) st8 [in9] = r10
70(p9) st8 [in10] = r11
71
72 mov gp = loc1
73 mov rp = loc2 ;;
74
75 mov ar.pfs = loc0
76 br.ret.sptk.many rp
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