source: mainline/boot/arch/ia64/loader/gefi/inc/pci22.h@ 86018c1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 86018c1 was 7208b6c, checked in by Jakub Vana <jakub.vana@…>, 17 years ago

Basic IA64 boot and kernel suport for real machines
  • Property mode set to 100644
File size: 4.5 KB
Line 
1#ifndef _PCI22_H
2#define _PCI22_H
3
4/*++
5
6Copyright (c) 1999 Intel Corporation
7
8Module Name:
9
10 pci22.h
11
12Abstract:
13 Support for PCI 2.2 standard.
14
15
16
17
18Revision History
19
20--*/
21
22#ifdef SOFT_SDV
23#define PCI_MAX_BUS 1
24#else
25#define PCI_MAX_BUS 255
26#endif
27
28#define PCI_MAX_DEVICE 31
29#define PCI_MAX_FUNC 7
30
31//
32// Command
33//
34#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
35
36#pragma pack(1)
37typedef struct {
38 UINT16 VendorId;
39 UINT16 DeviceId;
40 UINT16 Command;
41 UINT16 Status;
42 UINT8 RevisionID;
43 UINT8 ClassCode[3];
44 UINT8 CacheLineSize;
45 UINT8 LaytencyTimer;
46 UINT8 HeaderType;
47 UINT8 BIST;
48} PCI_DEVICE_INDEPENDENT_REGION;
49
50typedef struct {
51 UINT32 Bar[6];
52 UINT32 CISPtr;
53 UINT16 SubsystemVendorID;
54 UINT16 SubsystemID;
55 UINT32 ExpansionRomBar;
56 UINT32 Reserved[2];
57 UINT8 InterruptLine;
58 UINT8 InterruptPin;
59 UINT8 MinGnt;
60 UINT8 MaxLat;
61} PCI_DEVICE_HEADER_TYPE_REGION;
62
63typedef struct {
64 PCI_DEVICE_INDEPENDENT_REGION Hdr;
65 PCI_DEVICE_HEADER_TYPE_REGION Device;
66} PCI_TYPE00;
67
68typedef struct {
69 UINT32 Bar[2];
70 UINT8 PrimaryBus;
71 UINT8 SecondaryBus;
72 UINT8 SubordinateBus;
73 UINT8 SecondaryLatencyTimer;
74 UINT8 IoBase;
75 UINT8 IoLimit;
76 UINT16 SecondaryStatus;
77 UINT16 MemoryBase;
78 UINT16 MemoryLimit;
79 UINT16 PrefetchableMemoryBase;
80 UINT16 PrefetchableMemoryLimit;
81 UINT32 PrefetchableBaseUpper32;
82 UINT32 PrefetchableLimitUpper32;
83 UINT16 IoBaseUpper16;
84 UINT16 IoLimitUpper16;
85 UINT32 Reserved;
86 UINT32 ExpansionRomBAR;
87 UINT8 InterruptLine;
88 UINT8 InterruptPin;
89 UINT16 BridgeControl;
90} PCI_BRIDGE_CONTROL_REGISTER;
91
92#define PCI_CLASS_DISPLAY_CTRL 0x03
93#define PCI_CLASS_VGA 0x00
94
95#define PCI_CLASS_BRIDGE 0x06
96#define PCI_CLASS_ISA 0x01
97#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80
98
99#define PCI_CLASS_NETWORK 0x02
100#define PCI_CLASS_ETHERNET 0x00
101
102#define HEADER_TYPE_DEVICE 0x00
103#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
104#define HEADER_TYPE_MULTI_FUNCTION 0x80
105#define HEADER_LAYOUT_CODE 0x7f
106
107#define IS_PCI_BRIDGE(_p) ((((_p)->Hdr.HeaderType) & HEADER_LAYOUT_CODE) == HEADER_TYPE_PCI_TO_PCI_BRIDGE)
108#define IS_PCI_MULTI_FUNC(_p) (((_p)->Hdr.HeaderType) & HEADER_TYPE_MULTI_FUNCTION)
109
110typedef struct {
111 PCI_DEVICE_INDEPENDENT_REGION Hdr;
112 PCI_BRIDGE_CONTROL_REGISTER Bridge;
113} PCI_TYPE01;
114
115typedef struct {
116 UINT8 Register;
117 UINT8 Function;
118 UINT8 Device;
119 UINT8 Bus;
120 UINT8 Reserved[4];
121} DEFIO_PCI_ADDR;
122
123typedef struct {
124 UINT32 Reg : 8;
125 UINT32 Func : 3;
126 UINT32 Dev : 5;
127 UINT32 Bus : 8;
128 UINT32 Reserved: 7;
129 UINT32 Enable : 1;
130} PCI_CONFIG_ACCESS_CF8;
131
132#pragma pack()
133
134#define EFI_ROOT_BRIDGE_LIST 'eprb'
135typedef struct {
136 UINTN Signature;
137
138 UINT16 BridgeNumber;
139 UINT16 PrimaryBus;
140 UINT16 SubordinateBus;
141
142 EFI_DEVICE_PATH *DevicePath;
143
144 LIST_ENTRY Link;
145} PCI_ROOT_BRIDGE_ENTRY;
146
147
148#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
149#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
150#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32('P','C','I','R')
151
152#pragma pack(1)
153typedef struct {
154 UINT16 Signature; // 0xaa55
155 UINT8 Reserved[0x16];
156 UINT16 PcirOffset;
157} PCI_EXPANSION_ROM_HEADER;
158
159
160typedef struct {
161 UINT16 Signature; // 0xaa55
162 UINT16 InitializationSize;
163 UINT16 EfiSignature; // 0x0EF1
164 UINT16 EfiSubsystem;
165 UINT16 EfiMachineType;
166 UINT8 Reserved[0x0A];
167 UINT16 EfiImageHeaderOffset;
168 UINT16 PcirOffset;
169} EFI_PCI_EXPANSION_ROM_HEADER;
170
171typedef struct {
172 UINT32 Signature; // "PCIR"
173 UINT16 VendorId;
174 UINT16 DeviceId;
175 UINT16 Reserved0;
176 UINT16 Length;
177 UINT8 Revision;
178 UINT8 ClassCode[3];
179 UINT16 ImageLength;
180 UINT16 CodeRevision;
181 UINT8 CodeType;
182 UINT8 Indicator;
183 UINT16 Reserved1;
184} PCI_DATA_STRUCTURE;
185#pragma pack()
186
187#endif
188
189
190
191
192
193
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