source: mainline/boot/arch/arm32/src/asm.S@ b1011dae

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b1011dae was cfeb368, checked in by Jan Vesely <jano.vesely@…>, 13 years ago

arm32, boot: Remove redundant parameter.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1#
2# Copyright (c) 2007 Michal Kebrt
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/arch.h>
30
31.section BOOTSTRAP
32
33.global start
34.global boot_pt
35.global boot_stack
36.global halt
37.global jump_to_kernel
38
39start:
40 ldr sp, =boot_stack
41 b bootstrap
42
43.section BOOTPT
44boot_pt:
45 .space PTL0_ENTRIES * PTL0_ENTRY_SIZE
46
47.section BOOTSTACK
48 .space 4096
49boot_stack:
50
51.text
52
53halt:
54 b halt
55
56jump_to_kernel:
57 #
58 # TODO
59 # Make sure that the I-cache, D-cache and memory are mutually coherent
60 # before passing control to the copied code.
61 #
62
63 #
64 # r0 is kernel entry point
65 # r1 is pointer to the bootinfo structure
66
67#define CP15_C1_IC 12
68#define CP15_C1_BP 11
69#define CP15_C1_DC 2
70 # Disable I-cache and D-cache before the kernel is started.
71 mrc p15, 0, r4, c1, c0, 0
72 bic r4, r4, #(1 << CP15_C1_DC)
73 bic r4, r4, #(1 << CP15_C1_IC)
74 bic r4, r4, #(1 << CP15_C1_BP)
75 mcr p15, 0, r4, c1, c0, 0
76
77
78 #Wait for the operations to complete
79#ifdef PROCESSOR_ARCH_armv7_a
80 dsb
81#else
82 #cp15 dsb, r4 is ignored (should be zero)
83 mcr p15, 0, r4, c7, c10, 4
84#endif
85
86 # Clean ICache and BPredictors, r4 ignored (SBZ)
87 mcr p15, 0, r4, c7, c5, 0
88 nop
89
90 #Wait for the operations to complete
91#ifdef PROCESSOR_ARCH_armv7_a
92 isb
93 nop
94#else
95 # cp15 isb
96 mcr p15, 0, r4, c7, c5, 4
97 nop
98#endif
99
100#TODO:This should not be necessary
101
102#if defined(MACHINE_gta02)
103
104#define CP15_C7_SEG_SHIFT 5
105#define CP15_C7_SEG_SIZE 3
106#define CP15_C7_IDX_SHIFT 26
107
108 # Now clean D-cache to guarantee coherency between I-cache and D-cache.
109
110 # D-cache clean and invalidate procedure.
111 # See ARM920T TRM pages 2-17, 4-17.
112
113 # Initialize segment
114 mov r4, #0
115 # Initialize index
1161: mov r5, #0
1172: orr r6, r4, r5
118 # Clean and invalidate a single line
119 mcr p15, 0, r6, c7, c10, 2
120 # Increment index
121 add r5, r5, #(1 << CP15_C7_IDX_SHIFT)
122 cmp r5, #0
123 bne 2b
124 # Increment segment
125 add r4, #(1 << CP15_C7_SEG_SHIFT)
126 tst r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
127 beq 1b
128#endif
129
130 mov pc, r0
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