| 1 | /*
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| 2 | * Copyright (c) 2007 Michal Kebrt
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| 3 | * Copyright (c) 2010 Jiri Svoboda
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @addtogroup arm32boot
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| 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | * @brief Boot related declarations.
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| 35 | */
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| 36 |
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| 37 | #ifndef BOOT_arm32_MAIN_H
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| 38 | #define BOOT_arm32_MAIN_H
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| 39 |
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| 40 | /** Address where characters to be printed are expected. */
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| 41 |
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| 42 |
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| 43 | /** BeagleBoard-xM UART register address
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| 44 | *
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| 45 | * This is UART3 of AM/DM37x CPU
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| 46 | */
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| 47 | #define BBXM_SCONS_THR 0x49020000
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| 48 | #define BBXM_SCONS_SSR 0x49020044
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| 49 |
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| 50 | /* Check this bit before writing (tx fifo full) */
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| 51 | #define BBXM_THR_FULL 0x00000001
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| 52 |
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| 53 | /** Beaglebone UART register addresses
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| 54 | *
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| 55 | * This is UART0 of AM335x CPU
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| 56 | */
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| 57 | #define BBONE_SCONS_THR 0x44E09000
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| 58 | #define BBONE_SCONS_SSR 0x44E09044
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| 59 |
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| 60 | /** Check this bit before writing (tx fifo full) */
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| 61 | #define BBONE_TXFIFO_FULL 0x00000001
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| 62 |
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| 63 | /** GTA02 serial console UART register addresses.
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| 64 | *
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| 65 | * This is UART channel 2 of the S3C24xx CPU
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| 66 | */
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| 67 | #define GTA02_SCONS_UTRSTAT 0x50008010
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| 68 | #define GTA02_SCONS_UTXH 0x50008020
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| 69 |
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| 70 | /* Bits in UTXH register */
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| 71 | #define S3C24XX_UTXH_TX_EMPTY 0x00000004
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| 72 |
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| 73 |
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| 74 | /** IntegratorCP serial console output register */
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| 75 | #define ICP_SCONS_ADDR 0x16000000
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| 76 |
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| 77 | /** Raspberry PI serial console registers */
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| 78 | #define BCM2835_UART0_BASE 0x20201000
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| 79 | #define BCM2835_UART0_DR (BCM2835_UART0_BASE + 0x00)
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| 80 | #define BCM2835_UART0_FR (BCM2835_UART0_BASE + 0x18)
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| 81 | #define BCM2835_UART0_ILPR (BCM2835_UART0_BASE + 0x20)
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| 82 | #define BCM2835_UART0_IBRD (BCM2835_UART0_BASE + 0x24)
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| 83 | #define BCM2835_UART0_FBRD (BCM2835_UART0_BASE + 0x28)
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| 84 | #define BCM2835_UART0_LCRH (BCM2835_UART0_BASE + 0x2C)
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| 85 | #define BCM2835_UART0_CR (BCM2835_UART0_BASE + 0x30)
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| 86 | #define BCM2835_UART0_ICR (BCM2835_UART0_BASE + 0x44)
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| 87 |
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| 88 | #define BCM2835_UART0_FR_TXFF (1 << 5)
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| 89 | #define BCM2835_UART0_LCRH_FEN (1 << 4)
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| 90 | #define BCM2835_UART0_LCRH_WL8 ((1 << 5) | (1 << 6))
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| 91 | #define BCM2835_UART0_CR_UARTEN (1 << 0)
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| 92 | #define BCM2835_UART0_CR_TXE (1 << 8)
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| 93 | #define BCM2835_UART0_CR_RXE (1 << 9)
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| 94 |
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| 95 |
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| 96 |
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| 97 | extern void bootstrap(void);
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| 98 |
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| 99 | #endif
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| 100 |
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| 101 | /** @}
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| 102 | */
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