source: mainline/arch/sparc64/src/trap/exception.c@ ff14c520

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ff14c520 was 97f1691, checked in by Jakub Jermar <jakub@…>, 19 years ago

sparc64 work.
Fix KBD_VIRT_ADDRESS.
Call before_thread_runs() prior to the switch to the thread's stack. Add comment why this is crucial.
Add after_thread_ran() to the scheduler.
Add before_thread_runs_arch() and after_thread_ran_arch() for sparc64, mapping/demapping thread's kernel stack.
Add dummy after_thread_ran_arch() to all other architectures.
Add dtlb_insert_mapping() to promote code reuse.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/trap/exception.h>
30#include <arch/asm.h>
31#include <debug.h>
32
33/** Handle instruction_access_exception. */
34void do_instruction_access_exc(void)
35{
36 panic("Instruction Access Exception\n");
37}
38
39/** Handle mem_address_not_aligned. */
40void do_mem_address_not_aligned(void)
41{
42 panic("Memory Address Not Aligned\n");
43}
44
45/** Handle data_access_error. */
46void do_data_access_error(void)
47{
48 panic("Data Access Error: %P\n", tpc_read());
49}
50
51/** Handle mem_address_not_aligned. */
52void do_illegal_instruction(void)
53{
54 panic("Illegal Instruction: %P\n", tpc_read());
55}
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