source: mainline/arch/sparc64/src/mm/tlb.c@ 49b6d32

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 49b6d32 was 49b6d32, checked in by Jakub Jermar <jakub@…>, 20 years ago

sparc64 work.
Register window clean, spill and fill handlers.

  • Property mode set to 100644
File size: 5.2 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/mm/tlb.h>
30#include <mm/tlb.h>
31#include <arch/mm/frame.h>
32#include <arch/mm/page.h>
33#include <arch/mm/mmu.h>
34#include <print.h>
35#include <arch/types.h>
36#include <typedefs.h>
37#include <config.h>
38#include <arch/trap/trap.h>
39
40/** Initialize ITLB and DTLB.
41 *
42 * The goal of this function is to disable MMU
43 * so that both TLBs can be purged and new
44 * kernel 4M locked entry can be installed.
45 * After TLB is initialized, MMU is enabled
46 * again.
47 *
48 * Switching MMU off imposes the requirement for
49 * the kernel to run in identity mapped environment.
50 */
51void tlb_arch_init(void)
52{
53 tlb_tag_access_reg_t tag;
54 tlb_data_t data;
55 frame_address_t fr;
56 page_address_t pg;
57
58 fr.address = config.base;
59 pg.address = config.base;
60
61 immu_disable();
62 dmmu_disable();
63
64 /*
65 * For simplicity, we do identity mapping of first 4M of memory.
66 * The very next change should be leaving the first 4M unmapped.
67 */
68 tag.value = 0;
69 tag.vpn = pg.vpn;
70
71 itlb_tag_access_write(tag.value);
72 dtlb_tag_access_write(tag.value);
73
74 data.value = 0;
75 data.v = true;
76 data.size = PAGESIZE_4M;
77 data.pfn = fr.pfn;
78 data.l = true;
79 data.cp = 1;
80 data.cv = 1;
81 data.p = true;
82 data.w = true;
83 data.g = true;
84
85 itlb_data_in_write(data.value);
86 dtlb_data_in_write(data.value);
87
88 /*
89 * Register window traps can occur before MMU is enabled again.
90 * This ensures that any such traps will be handled from
91 * kernel identity mapped trap handler.
92 */
93 trap_switch_trap_table();
94
95 tlb_invalidate_all();
96
97 dmmu_enable();
98 immu_enable();
99}
100
101/** Print contents of both TLBs. */
102void tlb_print(void)
103{
104 int i;
105 tlb_data_t d;
106 tlb_tag_read_reg_t t;
107
108 printf("I-TLB contents:\n");
109 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
110 d.value = itlb_data_access_read(i);
111 t.value = itlb_tag_read_read(i);
112
113 printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
114 i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
115 }
116
117 printf("D-TLB contents:\n");
118 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
119 d.value = dtlb_data_access_read(i);
120 t.value = dtlb_tag_read_read(i);
121
122 printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
123 i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
124 }
125
126}
127
128/** Invalidate all unlocked ITLB and DTLB entries. */
129void tlb_invalidate_all(void)
130{
131 int i;
132 tlb_data_t d;
133 tlb_tag_read_reg_t t;
134
135 for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
136 d.value = itlb_data_access_read(i);
137 if (!d.l) {
138 t.value = itlb_tag_read_read(i);
139 d.v = false;
140 itlb_tag_access_write(t.value);
141 itlb_data_access_write(i, d.value);
142 }
143 }
144
145 for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
146 d.value = dtlb_data_access_read(i);
147 if (!d.l) {
148 t.value = dtlb_tag_read_read(i);
149 d.v = false;
150 dtlb_tag_access_write(t.value);
151 dtlb_data_access_write(i, d.value);
152 }
153 }
154
155}
156
157/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
158 *
159 * @param asid Address Space ID.
160 */
161void tlb_invalidate_asid(asid_t asid)
162{
163 /* TODO: write asid to some Context register and encode the register in second parameter below. */
164 itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
165 dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
166}
167
168/** Invalidate all ITLB and DLTB entries for specified page in specified address space.
169 *
170 * @param asid Address Space ID.
171 * @param page Page which to sweep out from ITLB and DTLB.
172 */
173void tlb_invalidate_page(asid_t asid, __address page)
174{
175 /* TODO: write asid to some Context register and encode the register in second parameter below. */
176 itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page);
177 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page);
178}
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