source: mainline/arch/sparc64/include/register.h@ 83d2d0e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 83d2d0e was 39494010, checked in by Jakub Jermar <jakub@…>, 20 years ago

sparc64 work.
Interrupt Levels 1 - 15 serviced.
Minor changes in the exc_* functions.

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __sparc64_REGISTER_H__
30#define __sparc64_REGISTER_H__
31
32#include <arch/types.h>
33
34/** Version Register. */
35union ver_reg {
36 __u64 value;
37 struct {
38 __u16 manuf; /**< Manufacturer code. */
39 __u16 impl; /**< Implementation code. */
40 __u8 mask; /**< Mask set revision. */
41 unsigned : 8;
42 __u8 maxtl;
43 unsigned : 3;
44 unsigned maxwin : 5;
45 } __attribute__ ((packed));
46};
47typedef union ver_reg ver_reg_t;
48
49/** Processor State Register. */
50union pstate_reg {
51 __u64 value;
52 struct {
53 __u64 : 52;
54 unsigned ig : 1; /**< Interrupt Globals. */
55 unsigned mg : 1; /**< MMU Globals. */
56 unsigned cle : 1; /**< Current Little Endian. */
57 unsigned tle : 1; /**< Trap Little Endian. */
58 unsigned mm : 2; /**< Memory Model. */
59 unsigned red : 1; /**< RED state. */
60 unsigned pef : 1; /**< Enable floating-point. */
61 unsigned am : 1; /**< 32-bit Address Mask. */
62 unsigned priv : 1; /**< Privileged Mode. */
63 unsigned ie : 1; /**< Interrupt Enable. */
64 unsigned ag : 1; /**< Alternate Globals*/
65 } __attribute__ ((packed));
66};
67typedef union pstate_reg pstate_reg_t;
68
69/** TICK Register. */
70union tick_reg {
71 __u64 value;
72 struct {
73 unsigned npt : 1; /**< Non-privileged Trap enable. */
74 __u64 counter : 63; /**< Elapsed CPU clck cycle counter. */
75 } __attribute__ ((packed));
76};
77typedef union tick_reg tick_reg_t;
78
79/** TICK_compare Register. */
80union tick_compare_reg {
81 __u64 value;
82 struct {
83 unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */
84 __u64 tick_cmpr : 63; /**< Compare value for TICK interrupts. */
85 } __attribute__ ((packed));
86};
87typedef union tick_compare_reg tick_compare_reg_t;
88
89/** SOFTINT Register. */
90union softint_reg {
91 __u64 value;
92 struct {
93 __u64 : 47;
94 unsigned stick_int : 1;
95 unsigned int_level : 15;
96 unsigned tick_int : 1;
97 } __attribute__ ((packed));
98};
99typedef union softint_reg softint_reg_t;
100
101#endif
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