source: mainline/arch/sparc64/include/barrier.h@ b5e0bb8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b5e0bb8 was b5e0bb8, checked in by Jakub Jermar <jakub@…>, 20 years ago

sparc64 bugfix.
When disabling IMMU and DMMU the kernel has to perform synchronization operation
(e.g flush %r or membar #Sync instruction). There is no guarantee that the address
contained in %r is in DTLB and therefore the flush instruction can fault. Normally
this would be recognized and fixed by the OpenFirmware Fast Data MMU fault handler.
However, this handler lives in virtually mapped memory and an attempt to execute
there while the MMUs are disabled would result in a nested trap leading to error state.
Replacing flush %r instruction with membar #Sync, wich is sufficient in this case,
fixes this problem.

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __sparc64_BARRIER_H__
30#define __sparc64_BARRIER_H__
31
32/*
33 * TODO: Implement true SPARC V9 memory barriers for macros below.
34 */
35#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
36#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
37
38#define memory_barrier()
39#define read_barrier()
40#define write_barrier()
41
42/** Flush Instruction Memory. */
43static inline void flush(void)
44{
45 /*
46 * The FLUSH instruction takes address parameter,
47 * but JPS1 implementations are free to ignore it.
48 * The only requirement is that it is a valid address
49 * as it is passed to D-MMU.
50 */
51 __asm__ volatile ("flush %sp\n"); /* %sp is guaranteed to reference mapped memory */
52}
53
54static inline void membar(void)
55{
56 __asm__ volatile ("membar #Sync\n");
57}
58
59#endif
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