[f761f1eb] | 1 | /*
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[178ec7b] | 2 | * Copyright (C) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <arch/mm/tlb.h>
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[0970f43] | 30 | #include <arch/mm/asid.h>
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[f761f1eb] | 31 | #include <mm/tlb.h>
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[1084a784] | 32 | #include <mm/page.h>
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| 33 | #include <mm/vm.h>
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[f761f1eb] | 34 | #include <arch/cp0.h>
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| 35 | #include <panic.h>
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| 36 | #include <arch.h>
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[ab08b42] | 37 | #include <symtab.h>
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[1084a784] | 38 | #include <synch/spinlock.h>
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| 39 | #include <print.h>
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[cc205f1] | 40 | #include <debug.h>
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[9c0a9b3] | 41 |
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[1084a784] | 42 | static void tlb_refill_fail(struct exception_regdump *pstate);
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| 43 | static void tlb_invalid_fail(struct exception_regdump *pstate);
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| 44 | static void tlb_modified_fail(struct exception_regdump *pstate);
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| 45 |
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[38a1a84] | 46 | static pte_t *find_mapping_and_check(__address badvaddr);
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[cc205f1] | 47 | static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn);
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[38a1a84] | 48 |
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[1084a784] | 49 | /** Initialize TLB
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| 50 | *
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| 51 | * Initialize TLB.
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| 52 | * Invalidate all entries and mark wired entries.
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| 53 | */
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[ce031f0] | 54 | void tlb_init_arch(void)
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| 55 | {
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| 56 | int i;
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| 57 |
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| 58 | cp0_pagemask_write(TLB_PAGE_MASK_16K);
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| 59 | cp0_entry_hi_write(0);
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| 60 | cp0_entry_lo0_write(0);
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| 61 | cp0_entry_lo1_write(0);
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| 62 |
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| 63 | /*
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| 64 | * Invalidate all entries.
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| 65 | */
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| 66 | for (i = 0; i < TLB_SIZE; i++) {
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[1084a784] | 67 | cp0_index_write(i);
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[ce031f0] | 68 | tlbwi();
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| 69 | }
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| 70 |
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| 71 | /*
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| 72 | * The kernel is going to make use of some wired
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[1084a784] | 73 | * entries (e.g. mapping kernel stacks in kseg3).
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[ce031f0] | 74 | */
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| 75 | cp0_wired_write(TLB_WIRED);
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| 76 | }
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| 77 |
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[1084a784] | 78 | /** Process TLB Refill Exception
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| 79 | *
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| 80 | * Process TLB Refill Exception.
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| 81 | *
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| 82 | * @param pstate Interrupted register context.
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| 83 | */
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[909c6e3] | 84 | void tlb_refill(struct exception_regdump *pstate)
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[1084a784] | 85 | {
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[cc205f1] | 86 | entry_lo_t lo;
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[1084a784] | 87 | __address badvaddr;
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| 88 | pte_t *pte;
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[fd3c9e5] | 89 |
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| 90 | // debug
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| 91 | entry_hi_t hi;
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| 92 |
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[1084a784] | 93 | badvaddr = cp0_badvaddr_read();
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[fd3c9e5] | 94 |
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| 95 | // debug
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| 96 | hi.value = cp0_entry_hi_read();
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| 97 | printf("TLB Refill: hi.vnp2=%X\n", hi.vpn2);
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[1084a784] | 98 |
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[38a1a84] | 99 | spinlock_lock(&VM->lock);
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| 100 | pte = find_mapping_and_check(badvaddr);
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[1084a784] | 101 | if (!pte)
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| 102 | goto fail;
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[38a1a84] | 103 |
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[1084a784] | 104 | /*
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[38a1a84] | 105 | * Record access to PTE.
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[1084a784] | 106 | */
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[38a1a84] | 107 | pte->a = 1;
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| 108 |
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| 109 | prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
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[1084a784] | 110 |
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| 111 | /*
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| 112 | * New entry is to be inserted into TLB
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| 113 | */
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| 114 | if ((badvaddr/PAGE_SIZE) % 2 == 0) {
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[cc205f1] | 115 | cp0_entry_lo0_write(lo.value);
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[1084a784] | 116 | cp0_entry_lo1_write(0);
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| 117 | }
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| 118 | else {
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| 119 | cp0_entry_lo0_write(0);
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[cc205f1] | 120 | cp0_entry_lo1_write(lo.value);
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[1084a784] | 121 | }
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| 122 | tlbwr();
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| 123 |
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| 124 | spinlock_unlock(&VM->lock);
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| 125 | return;
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| 126 |
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| 127 | fail:
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| 128 | spinlock_unlock(&VM->lock);
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| 129 | tlb_refill_fail(pstate);
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| 130 | }
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| 131 |
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[38a1a84] | 132 | /** Process TLB Invalid Exception
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| 133 | *
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| 134 | * Process TLB Invalid Exception.
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| 135 | *
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| 136 | * @param pstate Interrupted register context.
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| 137 | */
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[1084a784] | 138 | void tlb_invalid(struct exception_regdump *pstate)
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| 139 | {
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[cc205f1] | 140 | tlb_index_t index;
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[38a1a84] | 141 | __address badvaddr;
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[cc205f1] | 142 | entry_lo_t lo;
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[38a1a84] | 143 | pte_t *pte;
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| 144 |
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| 145 | badvaddr = cp0_badvaddr_read();
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| 146 |
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| 147 | /*
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| 148 | * Locate the faulting entry in TLB.
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| 149 | */
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| 150 | tlbp();
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[cc205f1] | 151 | index.value = cp0_index_read();
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[38a1a84] | 152 |
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| 153 | spinlock_lock(&VM->lock);
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| 154 |
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| 155 | /*
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| 156 | * Fail if the entry is not in TLB.
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| 157 | */
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[cc205f1] | 158 | if (index.p) {
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| 159 | printf("TLB entry not found.\n");
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[38a1a84] | 160 | goto fail;
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[cc205f1] | 161 | }
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[38a1a84] | 162 |
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| 163 | pte = find_mapping_and_check(badvaddr);
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| 164 | if (!pte)
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| 165 | goto fail;
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| 166 |
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| 167 | /*
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| 168 | * Read the faulting TLB entry.
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| 169 | */
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| 170 | tlbr();
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| 171 |
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| 172 | /*
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| 173 | * Record access to PTE.
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| 174 | */
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| 175 | pte->a = 1;
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| 176 |
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| 177 | prepare_entry_lo(&lo, pte->g, pte->v, pte->d, pte->c, pte->pfn);
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| 178 |
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| 179 | /*
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| 180 | * The entry is to be updated in TLB.
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| 181 | */
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| 182 | if ((badvaddr/PAGE_SIZE) % 2 == 0)
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[cc205f1] | 183 | cp0_entry_lo0_write(lo.value);
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[38a1a84] | 184 | else
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[cc205f1] | 185 | cp0_entry_lo1_write(lo.value);
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[38a1a84] | 186 | tlbwi();
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| 187 |
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| 188 | spinlock_unlock(&VM->lock);
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| 189 | return;
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| 190 |
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| 191 | fail:
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| 192 | spinlock_unlock(&VM->lock);
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[1084a784] | 193 | tlb_invalid_fail(pstate);
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| 194 | }
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| 195 |
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[38a1a84] | 196 | /** Process TLB Modified Exception
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| 197 | *
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| 198 | * Process TLB Modified Exception.
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| 199 | *
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| 200 | * @param pstate Interrupted register context.
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| 201 | */
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[1084a784] | 202 | void tlb_modified(struct exception_regdump *pstate)
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| 203 | {
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[cc205f1] | 204 | tlb_index_t index;
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[38a1a84] | 205 | __address badvaddr;
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[cc205f1] | 206 | entry_lo_t lo;
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[38a1a84] | 207 | pte_t *pte;
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| 208 |
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| 209 | badvaddr = cp0_badvaddr_read();
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| 210 |
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| 211 | /*
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| 212 | * Locate the faulting entry in TLB.
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| 213 | */
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| 214 | tlbp();
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[cc205f1] | 215 | index.value = cp0_index_read();
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[38a1a84] | 216 |
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| 217 | spinlock_lock(&VM->lock);
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| 218 |
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| 219 | /*
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| 220 | * Fail if the entry is not in TLB.
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| 221 | */
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[cc205f1] | 222 | if (index.p) {
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| 223 | printf("TLB entry not found.\n");
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[38a1a84] | 224 | goto fail;
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[cc205f1] | 225 | }
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[38a1a84] | 226 |
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| 227 | pte = find_mapping_and_check(badvaddr);
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| 228 | if (!pte)
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| 229 | goto fail;
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| 230 |
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| 231 | /*
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| 232 | * Fail if the page is not writable.
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| 233 | */
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| 234 | if (!pte->w)
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| 235 | goto fail;
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| 236 |
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| 237 | /*
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| 238 | * Read the faulting TLB entry.
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| 239 | */
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| 240 | tlbr();
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| 241 |
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| 242 | /*
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| 243 | * Record access and write to PTE.
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| 244 | */
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| 245 | pte->a = 1;
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| 246 | pte->d = 1;
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| 247 |
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| 248 | prepare_entry_lo(&lo, pte->g, pte->v, pte->w, pte->c, pte->pfn);
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| 249 |
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| 250 | /*
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| 251 | * The entry is to be updated in TLB.
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| 252 | */
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| 253 | if ((badvaddr/PAGE_SIZE) % 2 == 0)
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[cc205f1] | 254 | cp0_entry_lo0_write(lo.value);
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[38a1a84] | 255 | else
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[cc205f1] | 256 | cp0_entry_lo1_write(lo.value);
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[38a1a84] | 257 | tlbwi();
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| 258 |
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| 259 | spinlock_unlock(&VM->lock);
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| 260 | return;
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| 261 |
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| 262 | fail:
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| 263 | spinlock_unlock(&VM->lock);
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[1084a784] | 264 | tlb_modified_fail(pstate);
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| 265 | }
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| 266 |
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| 267 | void tlb_refill_fail(struct exception_regdump *pstate)
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[f761f1eb] | 268 | {
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[38de8a5] | 269 | char *symbol = "";
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| 270 | char *sym2 = "";
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| 271 |
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[3156582] | 272 | char *s = get_symtab_entry(pstate->epc);
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| 273 | if (s)
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| 274 | symbol = s;
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| 275 | s = get_symtab_entry(pstate->ra);
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| 276 | if (s)
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| 277 | sym2 = s;
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[1084a784] | 278 | panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), pstate->epc, symbol, sym2);
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[f761f1eb] | 279 | }
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| 280 |
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[1084a784] | 281 |
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| 282 | void tlb_invalid_fail(struct exception_regdump *pstate)
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[f761f1eb] | 283 | {
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[ab08b42] | 284 | char *symbol = "";
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| 285 |
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[3156582] | 286 | char *s = get_symtab_entry(pstate->epc);
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| 287 | if (s)
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| 288 | symbol = s;
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[38a1a84] | 289 | panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
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[f761f1eb] | 290 | }
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| 291 |
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[1084a784] | 292 | void tlb_modified_fail(struct exception_regdump *pstate)
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[ce031f0] | 293 | {
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| 294 | char *symbol = "";
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| 295 |
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| 296 | char *s = get_symtab_entry(pstate->epc);
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| 297 | if (s)
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| 298 | symbol = s;
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[38a1a84] | 299 | panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), pstate->epc, symbol);
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[ce031f0] | 300 | }
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| 301 |
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[cc205f1] | 302 | /** Invalidate TLB entries with specified ASID
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| 303 | *
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| 304 | * Invalidate TLB entries with specified ASID.
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| 305 | *
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| 306 | * @param asid ASID.
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| 307 | */
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| 308 | void tlb_invalidate(asid_t asid)
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[f761f1eb] | 309 | {
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[cc205f1] | 310 | entry_hi_t hi;
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[0970f43] | 311 | pri_t pri;
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[cc205f1] | 312 | int i;
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[0970f43] | 313 |
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[cc205f1] | 314 | ASSERT(asid != ASID_INVALID);
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| 315 |
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[0970f43] | 316 | pri = cpu_priority_high();
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| 317 |
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[cc205f1] | 318 | for (i = 0; i < TLB_SIZE; i++) {
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| 319 | cp0_index_write(i);
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| 320 | tlbr();
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| 321 |
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| 322 | hi.value = cp0_entry_hi_read();
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| 323 | if (hi.asid == asid) {
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| 324 | cp0_pagemask_write(TLB_PAGE_MASK_16K);
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| 325 | cp0_entry_hi_write(0);
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| 326 | cp0_entry_lo0_write(0);
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| 327 | cp0_entry_lo1_write(0);
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| 328 | tlbwi();
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| 329 | }
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| 330 | }
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[0970f43] | 331 |
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| 332 | cpu_priority_restore(pri);
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[f761f1eb] | 333 | }
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[38a1a84] | 334 |
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| 335 | /** Try to find PTE for faulting address
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| 336 | *
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| 337 | * Try to find PTE for faulting address.
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| 338 | * The VM->lock must be held on entry to this function.
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| 339 | *
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| 340 | * @param badvaddr Faulting virtual address.
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| 341 | *
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| 342 | * @return PTE on success, NULL otherwise.
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| 343 | */
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| 344 | pte_t *find_mapping_and_check(__address badvaddr)
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| 345 | {
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[cc205f1] | 346 | entry_hi_t hi;
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[38a1a84] | 347 | pte_t *pte;
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| 348 |
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[cc205f1] | 349 | hi.value = cp0_entry_hi_read();
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[38a1a84] | 350 |
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| 351 | /*
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| 352 | * Handler cannot succeed if the ASIDs don't match.
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| 353 | */
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[cc205f1] | 354 | if (hi.asid != VM->asid) {
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| 355 | printf("EntryHi.asid=%d, VM->asid=%d\n", hi.asid, VM->asid);
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[38a1a84] | 356 | return NULL;
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[cc205f1] | 357 | }
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[38a1a84] | 358 |
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| 359 | /*
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| 360 | * Handler cannot succeed if badvaddr has no mapping.
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| 361 | */
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| 362 | pte = find_mapping(badvaddr, 0);
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[cc205f1] | 363 | if (!pte) {
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| 364 | printf("No such mapping.\n");
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[38a1a84] | 365 | return NULL;
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[cc205f1] | 366 | }
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[38a1a84] | 367 |
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| 368 | /*
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| 369 | * Handler cannot succeed if the mapping is marked as invalid.
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| 370 | */
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[cc205f1] | 371 | if (!pte->v) {
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| 372 | printf("Invalid mapping.\n");
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[38a1a84] | 373 | return NULL;
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[cc205f1] | 374 | }
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[38a1a84] | 375 |
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| 376 | return pte;
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| 377 | }
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| 378 |
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[cc205f1] | 379 | void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn)
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[38a1a84] | 380 | {
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| 381 | lo->g = g;
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| 382 | lo->v = v;
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| 383 | lo->d = d;
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| 384 | lo->c = c;
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| 385 | lo->pfn = pfn;
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| 386 | lo->zero = 0;
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| 387 | }
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