source: mainline/arch/mips32/src/mips32.c@ b45c443

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b45c443 was b45c443, checked in by Josef Cejka <malyzelenyhnus@…>, 19 years ago

Kernel doxygen comments updated.

  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /** @addtogroup mips32
30 * @ingroup others
31 * @{
32 */
33/** @file
34 */
35
36
37#include <arch.h>
38#include <arch/boot.h>
39#include <arch/cp0.h>
40#include <arch/exception.h>
41#include <arch/asm.h>
42#include <mm/as.h>
43
44#include <userspace.h>
45#include <arch/console.h>
46#include <memstr.h>
47#include <proc/thread.h>
48#include <proc/uarg.h>
49#include <print.h>
50#include <syscall/syscall.h>
51#include <sysinfo/sysinfo.h>
52
53#include <arch/interrupt.h>
54#include <arch/drivers/arc.h>
55#include <console/chardev.h>
56#include <arch/debugger.h>
57#include <genarch/fb/fb.h>
58#include <debug.h>
59
60#include <arch/asm/regname.h>
61
62/* Size of the code jumping to the exception handler code
63 * - J+NOP
64 */
65#define EXCEPTION_JUMP_SIZE 8
66
67#define TLB_EXC ((char *) 0x80000000)
68#define NORM_EXC ((char *) 0x80000180)
69#define CACHE_EXC ((char *) 0x80000100)
70
71bootinfo_t bootinfo;
72
73void arch_pre_main(void)
74{
75 /* Setup usermode */
76 init.cnt = bootinfo.cnt;
77
78 __u32 i;
79
80 for (i = 0; i < bootinfo.cnt; i++) {
81 init.tasks[i].addr = bootinfo.tasks[i].addr;
82 init.tasks[i].size = bootinfo.tasks[i].size;
83 }
84}
85
86void arch_pre_mm_init(void)
87{
88 /* It is not assumed by default */
89 interrupts_disable();
90
91 /* Initialize dispatch table */
92 exception_init();
93 arc_init();
94
95 /* Copy the exception vectors to the right places */
96 memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
97 memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
98 memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
99
100 interrupt_init();
101 /*
102 * Switch to BEV normal level so that exception vectors point to the kernel.
103 * Clear the error level.
104 */
105 cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
106
107 /*
108 * Mask all interrupts
109 */
110 cp0_mask_all_int();
111
112 /*
113 * Unmask hardware clock interrupt.
114 */
115 cp0_unmask_int(TIMER_IRQ);
116
117 console_init();
118 debugger_init();
119}
120
121void arch_post_mm_init(void)
122{
123#ifdef CONFIG_FB
124 fb_init(0x12000000, 640, 480, 24, 1920); // gxemul framebuffer
125#endif
126 sysinfo_set_item_val("machine." STRING(MACHINE),NULL,1);
127}
128
129void arch_pre_smp_init(void)
130{
131}
132
133void arch_post_smp_init(void)
134{
135}
136
137/* Stack pointer saved when entering user mode */
138/* TODO: How do we do it on SMP system???? */
139
140/* Why the linker moves the variable 64K away in assembler
141 * when not in .text section ????????
142 */
143__address supervisor_sp __attribute__ ((section (".text")));
144
145void userspace(uspace_arg_t *kernel_uarg)
146{
147 /* EXL=1, UM=1, IE=1 */
148 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
149 cp0_status_um_bit |
150 cp0_status_ie_enabled_bit));
151 cp0_epc_write((__address) kernel_uarg->uspace_entry);
152 userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE),
153 (__address) kernel_uarg->uspace_uarg,
154 (__address) kernel_uarg->uspace_entry);
155 while (1)
156 ;
157}
158
159/** Perform mips32 specific tasks needed before the new task is run. */
160void before_task_runs_arch(void)
161{
162}
163
164/** Perform mips32 specific tasks needed before the new thread is scheduled. */
165void before_thread_runs_arch(void)
166{
167 supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
168}
169
170void after_thread_ran_arch(void)
171{
172}
173
174/** Set thread-local-storage pointer
175 *
176 * We have it currently in K1, it is
177 * possible to have it separately in the future.
178 */
179__native sys_tls_set(__native addr)
180{
181 return 0;
182}
183
184
185 /** @}
186 */
187
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