source: mainline/arch/mips32/src/mips32.c@ 9aa72b4

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9aa72b4 was 0f250f9, checked in by Jakub Jermar <jakub@…>, 20 years ago

Improved uspace threads.
ia64 needs fixing.

  • Property mode set to 100644
File size: 3.9 KB
RevLine 
[f761f1eb]1/*
[178ec7b]2 * Copyright (C) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[973be64e]29
[f761f1eb]30#include <arch.h>
31#include <arch/cp0.h>
32#include <arch/exception.h>
[2bd4fdf]33#include <arch/asm.h>
[20d50a1]34#include <mm/as.h>
[973be64e]35
[2bd4fdf]36#include <userspace.h>
[38de8a5]37#include <arch/console.h>
[ffc277e]38#include <memstr.h>
[1084a784]39#include <proc/thread.h>
[0f250f9]40#include <proc/uarg.h>
[a1493d9]41#include <print.h>
42
[973be64e]43#include <arch/interrupt.h>
44#include <arch/drivers/arc.h>
45#include <console/chardev.h>
[5bb8e45]46#include <arch/debugger.h>
[973be64e]47
48#include <arch/asm/regname.h>
49
[ffc277e]50/* Size of the code jumping to the exception handler code
51 * - J+NOP
52 */
53#define EXCEPTION_JUMP_SIZE 8
54
55#define TLB_EXC ((char *) 0x80000000)
56#define NORM_EXC ((char *) 0x80000180)
57#define CACHE_EXC ((char *) 0x80000100)
58
[f07bba5]59void arch_pre_mm_init(void)
[f761f1eb]60{
[24241cf]61 /* It is not assumed by default */
[22f7769]62 interrupts_disable();
[973be64e]63
64 /* Initialize dispatch table */
[7a8c866a]65 exception_init();
[973be64e]66 interrupt_init();
[24241cf]67
[939dfd7]68 arc_init();
[3156582]69
[ffc277e]70 /* Copy the exception vectors to the right places */
71 memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
72 memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
73 memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
74
[f761f1eb]75 /*
76 * Switch to BEV normal level so that exception vectors point to the kernel.
77 * Clear the error level.
78 */
79 cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
[76cec1e]80
[24241cf]81 /*
82 * Mask all interrupts
83 */
84 cp0_mask_all_int();
[f761f1eb]85 /*
86 * Unmask hardware clock interrupt.
87 */
[a7fdfe1]88 cp0_unmask_int(TIMER_IRQ);
[76cec1e]89
[f761f1eb]90 /*
91 * Start hardware clock.
92 */
[38de8a5]93 cp0_compare_write(cp0_compare_value + cp0_count_read());
94
95 console_init();
[5bb8e45]96 debugger_init();
[b6b576c]97
98 /* Setup usermode */
99 init.cnt = 1;
100 init.tasks[0].addr = INIT_ADDRESS;
101 init.tasks[0].size = INIT_SIZE;
[f761f1eb]102}
[7eade45]103
104void arch_post_mm_init(void)
105{
106}
[babcb148]107
[7453929]108void arch_pre_smp_init(void)
109{
110}
111
112void arch_post_smp_init(void)
[babcb148]113{
114}
[2bd4fdf]115
[021d471]116/* Stack pointer saved when entering user mode */
117/* TODO: How do we do it on SMP system???? */
118
[8b3eebb]119/* Why the linker moves the variable 64K away in assembler
[021d471]120 * when not in .text section ????????
121 */
122__address supervisor_sp __attribute__ ((section (".text")));
123
[0f250f9]124void userspace(uspace_arg_t *kernel_uarg)
[2bd4fdf]125{
126 /* EXL=1, UM=1, IE=1 */
127 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
128 cp0_status_um_bit |
129 cp0_status_ie_enabled_bit));
[0f250f9]130 cp0_epc_write((__address) kernel_uarg->uspace_entry);
131 userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE), (__address) kernel_uarg->uspace_uarg);
[2bd4fdf]132 while (1)
133 ;
134}
135
136void before_thread_runs_arch(void)
137{
138 supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
139}
[97f1691]140
141void after_thread_ran_arch(void)
142{
143}
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