source: mainline/arch/mips32/src/mips32.c@ 3d2d2fc2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3d2d2fc2 was 3d2d2fc2, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

Fixed uspace address constants.

  • Property mode set to 100644
File size: 3.8 KB
RevLine 
[f761f1eb]1/*
[178ec7b]2 * Copyright (C) 2003-2004 Jakub Jermar
[f761f1eb]3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
[973be64e]29
[f761f1eb]30#include <arch.h>
31#include <arch/cp0.h>
32#include <arch/exception.h>
[2bd4fdf]33#include <arch/asm.h>
[20d50a1]34#include <mm/as.h>
[973be64e]35
[2bd4fdf]36#include <userspace.h>
[38de8a5]37#include <arch/console.h>
[ffc277e]38#include <memstr.h>
[1084a784]39#include <proc/thread.h>
[a1493d9]40#include <print.h>
41
[973be64e]42#include <arch/interrupt.h>
43#include <arch/drivers/arc.h>
44#include <console/chardev.h>
[5bb8e45]45#include <arch/debugger.h>
[973be64e]46
47#include <arch/asm/regname.h>
48
[ffc277e]49/* Size of the code jumping to the exception handler code
50 * - J+NOP
51 */
52#define EXCEPTION_JUMP_SIZE 8
53
54#define TLB_EXC ((char *) 0x80000000)
55#define NORM_EXC ((char *) 0x80000180)
56#define CACHE_EXC ((char *) 0x80000100)
57
[f07bba5]58void arch_pre_mm_init(void)
[f761f1eb]59{
[24241cf]60 /* It is not assumed by default */
[22f7769]61 interrupts_disable();
[973be64e]62
63 /* Initialize dispatch table */
[7a8c866a]64 exception_init();
[973be64e]65 interrupt_init();
[24241cf]66
[939dfd7]67 arc_init();
[3156582]68
[ffc277e]69 /* Copy the exception vectors to the right places */
70 memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
71 memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
72 memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
73
[f761f1eb]74 /*
75 * Switch to BEV normal level so that exception vectors point to the kernel.
76 * Clear the error level.
77 */
78 cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
[76cec1e]79
[24241cf]80 /*
81 * Mask all interrupts
82 */
83 cp0_mask_all_int();
[f761f1eb]84 /*
85 * Unmask hardware clock interrupt.
86 */
[a7fdfe1]87 cp0_unmask_int(TIMER_IRQ);
[76cec1e]88
[f761f1eb]89 /*
90 * Start hardware clock.
91 */
[38de8a5]92 cp0_compare_write(cp0_compare_value + cp0_count_read());
93
94 console_init();
[5bb8e45]95 debugger_init();
[3156582]96 arc_print_memory_map();
[c7a7656]97 arc_print_devices();
[f761f1eb]98}
[7eade45]99
100void arch_post_mm_init(void)
101{
[3d2d2fc2]102 /* Setup usermode...*/
103 config.init_addr = INIT_ADDRESS;
104 config.init_size = INIT_SIZE;
[7eade45]105}
[babcb148]106
[7453929]107void arch_pre_smp_init(void)
108{
109}
110
111void arch_post_smp_init(void)
[babcb148]112{
113}
[2bd4fdf]114
[021d471]115/* Stack pointer saved when entering user mode */
116/* TODO: How do we do it on SMP system???? */
117
118/* Why the hell moves the linker the variable 64K away in assembler
119 * when not in .text section ????????
120 */
121__address supervisor_sp __attribute__ ((section (".text")));
122
[2bd4fdf]123void userspace(void)
124{
125 /* EXL=1, UM=1, IE=1 */
126 cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
127 cp0_status_um_bit |
128 cp0_status_ie_enabled_bit));
129
130 cp0_epc_write(UTEXT_ADDRESS);
131 userspace_asm(USTACK_ADDRESS+PAGE_SIZE);
132 while (1)
133 ;
134}
135
136void before_thread_runs_arch(void)
137{
138 supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
139}
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