source: mainline/arch/mips32/src/exception.c@ e07fe0c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e07fe0c was e07fe0c, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

added support for breakpoints to mips32

  • Property mode set to 100644
File size: 5.6 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/exception.h>
30#include <arch/interrupt.h>
31#include <panic.h>
32#include <arch/cp0.h>
33#include <arch/types.h>
34#include <arch.h>
35#include <debug.h>
36#include <proc/thread.h>
37#include <symtab.h>
38#include <print.h>
39#include <interrupt.h>
40#include <func.h>
41#include <console/kconsole.h>
42
43static char * exctable[] = {
44 "Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store",
45 "Address Error - load/instr. fetch",
46 "Address Error - store",
47 "Bus Error - fetch instruction",
48 "Bus Error - data reference",
49 "Syscall",
50 "BreakPoint",
51 "Reserved Instruction",
52 "Coprocessor Unusable",
53 "Arithmetic Overflow",
54 "Trap",
55 "Virtual Coherency - instruction",
56 "Floating Point",
57 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
58 "WatchHi/WatchLo", /* 23 */
59 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
60 "Virtual Coherency - data",
61};
62
63static void print_regdump(struct exception_regdump *pstate)
64{
65 char *pcsymbol = "";
66 char *rasymbol = "";
67
68 char *s = get_symtab_entry(pstate->epc);
69 if (s)
70 pcsymbol = s;
71 s = get_symtab_entry(pstate->ra);
72 if (s)
73 rasymbol = s;
74
75 printf("PC: %X(%s) RA: %X(%s)\n",pstate->epc,pcsymbol,
76 pstate->ra,rasymbol);
77}
78
79static void unhandled_exception(int n, void *data)
80{
81 struct exception_regdump *pstate = (struct exception_regdump *)data;
82
83 print_regdump(pstate);
84 panic("unhandled exception %s\n", exctable[n]);
85}
86
87static void breakpoint_exception(int n, void *data)
88{
89 struct exception_regdump *pstate = (struct exception_regdump *)data;
90 char *symbol = get_symtab_entry(pstate->epc);
91
92#ifdef CONFIG_DEBUG
93 printf("***Breakpoint %p in %s.\n", pstate->epc, symbol);
94 printf("***Type 'exit' to exit kconsole.\n");
95 /* Umm..we should rather set some 'debugstate' here */
96 haltstate = 1;
97 kconsole("debug");
98 haltstate = 0;
99#endif
100
101 /* it is necessary to not re-execute BREAK instruction after
102 returning from Exception handler
103 (see page 138 in R4000 Manual for more information) */
104 pstate->epc += 4;
105}
106
107static void tlbmod_exception(int n, void *data)
108{
109 struct exception_regdump *pstate = (struct exception_regdump *)data;
110 tlb_modified(pstate);
111}
112
113static void tlbinv_exception(int n, void *data)
114{
115 struct exception_regdump *pstate = (struct exception_regdump *)data;
116 tlb_invalid(pstate);
117}
118
119static void cpuns_exception(int n, void *data)
120{
121 if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
122 scheduler_fpu_lazy_request();
123 else
124 panic("unhandled Coprocessor Unusable Exception\n");
125}
126
127static void interrupt_exception(int n, void *pstate)
128{
129 __u32 cause;
130 int i;
131
132 /* decode interrupt number and process the interrupt */
133 cause = (cp0_cause_read() >> 8) &0xff;
134
135 for (i = 0; i < 8; i++)
136 if (cause & (1 << i))
137 exc_dispatch(i+INT_OFFSET, pstate);
138}
139
140
141void exception(struct exception_regdump *pstate)
142{
143 int cause;
144 int excno;
145 __u32 epc_shift = 0;
146
147 ASSERT(CPU != NULL);
148
149 /*
150 * NOTE ON OPERATION ORDERING
151 *
152 * On entry, interrupts_disable() must be called before
153 * exception bit is cleared.
154 */
155
156 interrupts_disable();
157 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
158 cp0_status_um_bit));
159
160 /* Save pstate so that the threads can access it */
161 /* If THREAD->pstate is set, this is nested exception,
162 * do not rewrite it
163 */
164 if (THREAD && !THREAD->pstate)
165 THREAD->pstate = pstate;
166
167 cause = cp0_cause_read();
168 excno = cp0_cause_excno(cause);
169 /* Dispatch exception */
170 exc_dispatch(excno, pstate);
171
172 /* Set to NULL, so that we can still support nested
173 * exceptions
174 * TODO: We should probably set EXL bit before this command,
175 * nesting. On the other hand, if some exception occurs between
176 * here and ERET, it won't set anything on the pstate anyway.
177 */
178 if (THREAD)
179 THREAD->pstate = NULL;
180}
181
182void exception_init(void)
183{
184 int i;
185
186 /* Clear exception table */
187 for (i=0;i < IVT_ITEMS; i++)
188 exc_register(i, "undef", unhandled_exception);
189 exc_register(EXC_Bp, "bkpoint", breakpoint_exception);
190 exc_register(EXC_Mod, "tlb_mod", tlbmod_exception);
191 exc_register(EXC_TLBL, "tlbinvl", tlbinv_exception);
192 exc_register(EXC_TLBS, "tlbinvl", tlbinv_exception);
193 exc_register(EXC_Int, "interrupt", interrupt_exception);
194#ifdef CONFIG_FPU_LAZY
195 exc_register(EXC_CpU, "cpunus", cpuns_exception);
196#endif
197}
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