source: mainline/arch/mips32/src/exception.c@ 49c1f93

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 49c1f93 was 1084a784, checked in by Jakub Jermar <jakub@…>, 20 years ago

mips32 memory management work.
TLB Refill Exception implemented (passed basic testing).
Remove bit g from struct entry_hi.
Add generic find_mapping().
Add asid to vm_t type, define asid_t to hide architecture specific differences.
Implement ASID allocation for mips32, dummy for other architectures.
Add THE→vm (a.k.a. VM).
Add vm_install_arch().
Move pte_t definition to arch/types.h on each architecture.
Fix PTL manipulating functions on mips32 to shift pfn by 12 instead of by 14.
Fix tlb_init_arch() to initialize all entries.

Other.
Remove unnecessary header files from arch.h
Add missing headers here and there.
Remove two unnecessary ld flags from mips32 makefile.
  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/exception.h>
30#include <arch/interrupt.h>
31#include <panic.h>
32#include <arch/cp0.h>
33#include <arch/types.h>
34#include <arch.h>
35#include <debug.h>
36#include <proc/thread.h>
37
38void exception(struct exception_regdump *pstate)
39{
40 int cause;
41 int excno;
42 __u32 epc_shift = 0;
43
44 ASSERT(CPU != NULL);
45
46 /*
47 * NOTE ON OPERATION ORDERING
48 *
49 * On entry, cpu_priority_high() must be called before
50 * exception bit is cleared.
51 */
52
53 cpu_priority_high();
54 cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
55 cp0_status_um_bit));
56
57 /* Save pstate so that the threads can access it */
58 /* If THREAD->pstate is set, this is nested exception,
59 * do not rewrite it
60 */
61 if (THREAD && !THREAD->pstate)
62 THREAD->pstate = pstate;
63
64 cause = cp0_cause_read();
65 excno = cp0_cause_excno(cause);
66 /* decode exception number and process the exception */
67 switch (excno) {
68 case EXC_Int:
69 interrupt(pstate);
70 break;
71 case EXC_TLBL:
72 case EXC_TLBS:
73 tlb_invalid(pstate);
74 break;
75 case EXC_CpU:
76#ifdef FPU_LAZY
77 if (cp0_cause_coperr(cause) == fpu_cop_id)
78 scheduler_fpu_lazy_request();
79 else
80#endif
81 panic("unhandled Coprocessor Unusable Exception\n");
82 break;
83 case EXC_Mod:
84 tlb_modified(pstate);
85 break;
86 case EXC_AdEL:
87 panic("unhandled Address Error Exception - load or instruction fetch\n");
88 break;
89 case EXC_AdES:
90 panic("unhandled Address Error Exception - store\n");
91 break;
92 case EXC_IBE:
93 panic("unhandled Bus Error Exception - fetch instruction\n");
94 break;
95 case EXC_DBE:
96 panic("unhandled Bus Error Exception - data reference: load or store\n");
97 break;
98 case EXC_Bp:
99 /* it is necessary to not re-execute BREAK instruction after returning from Exception handler
100 (see page 138 in R4000 Manual for more information) */
101 epc_shift = 4;
102 break;
103 case EXC_RI:
104 panic("unhandled Reserved Instruction Exception\n");
105 break;
106 case EXC_Ov:
107 panic("unhandled Arithmetic Overflow Exception\n");
108 break;
109 case EXC_Tr:
110 panic("unhandled Trap Exception\n");
111 break;
112 case EXC_VCEI:
113 panic("unhandled Virtual Coherency Exception - instruction\n");
114 break;
115 case EXC_FPE:
116 panic("unhandled Floating-Point Exception\n");
117 break;
118 case EXC_WATCH:
119 panic("unhandled reference to WatchHi/WatchLo address\n");
120 break;
121 case EXC_VCED:
122 panic("unhandled Virtual Coherency Exception - data\n");
123 break;
124 default:
125 panic("unhandled exception %d\n", excno);
126 }
127
128 pstate->epc += epc_shift;
129 /* Set to NULL, so that we can still support nested
130 * exceptions
131 * TODO: We should probably set EXL bit before this command,
132 * nesting. On the other hand, if some exception occurs between
133 * here and ERET, it won't set anything on the pstate anyway.
134 */
135 if (THREAD)
136 THREAD->pstate = NULL;
137}
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