[f761f1eb] | 1 | /*
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[178ec7b] | 2 | * Copyright (C) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #include <arch/exception.h>
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[9c0a9b3] | 30 | #include <arch/interrupt.h>
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[f761f1eb] | 31 | #include <panic.h>
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| 32 | #include <arch/cp0.h>
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| 33 | #include <arch/types.h>
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| 34 | #include <arch.h>
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[623ba26c] | 35 | #include <debug.h>
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[1084a784] | 36 | #include <proc/thread.h>
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[7a8c866a] | 37 | #include <symtab.h>
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| 38 | #include <print.h>
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| 39 | #include <interrupt.h>
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[e07fe0c] | 40 | #include <func.h>
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| 41 | #include <console/kconsole.h>
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[5bb8e45] | 42 | #include <arch/debugger.h>
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[021d471] | 43 | #include <syscall/syscall.h>
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[7a8c866a] | 44 |
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| 45 | static char * exctable[] = {
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| 46 | "Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store",
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| 47 | "Address Error - load/instr. fetch",
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| 48 | "Address Error - store",
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| 49 | "Bus Error - fetch instruction",
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| 50 | "Bus Error - data reference",
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| 51 | "Syscall",
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| 52 | "BreakPoint",
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| 53 | "Reserved Instruction",
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| 54 | "Coprocessor Unusable",
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| 55 | "Arithmetic Overflow",
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| 56 | "Trap",
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| 57 | "Virtual Coherency - instruction",
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| 58 | "Floating Point",
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| 59 | NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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| 60 | "WatchHi/WatchLo", /* 23 */
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| 61 | NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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| 62 | "Virtual Coherency - data",
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| 63 | };
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| 64 |
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| 65 | static void print_regdump(struct exception_regdump *pstate)
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| 66 | {
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| 67 | char *pcsymbol = "";
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| 68 | char *rasymbol = "";
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| 69 |
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| 70 | char *s = get_symtab_entry(pstate->epc);
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| 71 | if (s)
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| 72 | pcsymbol = s;
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| 73 | s = get_symtab_entry(pstate->ra);
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| 74 | if (s)
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| 75 | rasymbol = s;
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| 76 |
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[052da81] | 77 | printf("PC: %X(%s) RA: %X(%s), SP(%P)\n",pstate->epc,pcsymbol,
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| 78 | pstate->ra,rasymbol, pstate->sp);
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[7a8c866a] | 79 | }
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| 80 |
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[49a39c2] | 81 | static void unhandled_exception(int n, struct exception_regdump *pstate)
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[7a8c866a] | 82 | {
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| 83 | print_regdump(pstate);
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| 84 | panic("unhandled exception %s\n", exctable[n]);
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| 85 | }
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| 86 |
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[49a39c2] | 87 | static void breakpoint_exception(int n, struct exception_regdump *pstate)
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[7a8c866a] | 88 | {
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[5bb8e45] | 89 | #ifdef CONFIG_DEBUG
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| 90 | debugger_bpoint(pstate);
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| 91 | #else
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[7a8c866a] | 92 | /* it is necessary to not re-execute BREAK instruction after
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| 93 | returning from Exception handler
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| 94 | (see page 138 in R4000 Manual for more information) */
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| 95 | pstate->epc += 4;
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[5bb8e45] | 96 | #endif
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[7a8c866a] | 97 | }
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| 98 |
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[49a39c2] | 99 | static void tlbmod_exception(int n, struct exception_regdump *pstate)
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[7a8c866a] | 100 | {
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| 101 | tlb_modified(pstate);
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| 102 | }
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| 103 |
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[49a39c2] | 104 | static void tlbinv_exception(int n, struct exception_regdump *pstate)
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[7a8c866a] | 105 | {
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| 106 | tlb_invalid(pstate);
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| 107 | }
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| 108 |
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[5a95b25] | 109 | #ifdef CONFIG_FPU_LAZY
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[49a39c2] | 110 | static void cpuns_exception(int n, struct exception_regdump *pstate)
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[7a8c866a] | 111 | {
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| 112 | if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
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| 113 | scheduler_fpu_lazy_request();
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| 114 | else
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| 115 | panic("unhandled Coprocessor Unusable Exception\n");
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| 116 | }
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[5a95b25] | 117 | #endif
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[7a8c866a] | 118 |
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[49a39c2] | 119 | static void interrupt_exception(int n, struct exception_regdump *pstate)
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[7a8c866a] | 120 | {
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| 121 | __u32 cause;
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| 122 | int i;
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| 123 |
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| 124 | /* decode interrupt number and process the interrupt */
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| 125 | cause = (cp0_cause_read() >> 8) &0xff;
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| 126 |
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| 127 | for (i = 0; i < 8; i++)
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| 128 | if (cause & (1 << i))
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| 129 | exc_dispatch(i+INT_OFFSET, pstate);
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| 130 | }
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| 131 |
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[021d471] | 132 | #include <debug.h>
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| 133 | /** Handle syscall userspace call */
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[49a39c2] | 134 | static void syscall_exception(int n, struct exception_regdump *pstate)
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[021d471] | 135 | {
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| 136 | if (pstate->a3 < SYSCALL_END)
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| 137 | pstate->v0 = syscall_table[pstate->a3](pstate->a0,
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| 138 | pstate->a1,
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| 139 | pstate->a2);
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| 140 | else
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| 141 | panic("Undefined syscall %d", pstate->a3);
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| 142 | pstate->epc += 4;
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| 143 | }
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| 144 |
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[f761f1eb] | 145 |
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[909c6e3] | 146 | void exception(struct exception_regdump *pstate)
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[f761f1eb] | 147 | {
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[a1493d9] | 148 | int cause;
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[f761f1eb] | 149 | int excno;
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[3e1607f] | 150 |
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[623ba26c] | 151 | ASSERT(CPU != NULL);
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| 152 |
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[3e1607f] | 153 | /*
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| 154 | * NOTE ON OPERATION ORDERING
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| 155 | *
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[22f7769] | 156 | * On entry, interrupts_disable() must be called before
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[909c6e3] | 157 | * exception bit is cleared.
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[3e1607f] | 158 | */
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| 159 |
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[22f7769] | 160 | interrupts_disable();
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[2bd4fdf] | 161 | cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
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| 162 | cp0_status_um_bit));
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[f3a6c8e5] | 163 |
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[ffc277e] | 164 | /* Save pstate so that the threads can access it */
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[f3a6c8e5] | 165 | /* If THREAD->pstate is set, this is nested exception,
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| 166 | * do not rewrite it
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| 167 | */
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| 168 | if (THREAD && !THREAD->pstate)
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[ffc277e] | 169 | THREAD->pstate = pstate;
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[f761f1eb] | 170 |
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[a1493d9] | 171 | cause = cp0_cause_read();
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| 172 | excno = cp0_cause_excno(cause);
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[7a8c866a] | 173 | /* Dispatch exception */
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| 174 | exc_dispatch(excno, pstate);
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| 175 |
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[f3a6c8e5] | 176 | /* Set to NULL, so that we can still support nested
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| 177 | * exceptions
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| 178 | * TODO: We should probably set EXL bit before this command,
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| 179 | * nesting. On the other hand, if some exception occurs between
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| 180 | * here and ERET, it won't set anything on the pstate anyway.
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| 181 | */
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[ffc277e] | 182 | if (THREAD)
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| 183 | THREAD->pstate = NULL;
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[f761f1eb] | 184 | }
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[7a8c866a] | 185 |
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| 186 | void exception_init(void)
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| 187 | {
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| 188 | int i;
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| 189 |
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| 190 | /* Clear exception table */
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| 191 | for (i=0;i < IVT_ITEMS; i++)
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[49a39c2] | 192 | exc_register(i, "undef", (iroutine) unhandled_exception);
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| 193 | exc_register(EXC_Bp, "bkpoint", (iroutine) breakpoint_exception);
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| 194 | exc_register(EXC_Mod, "tlb_mod", (iroutine) tlbmod_exception);
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| 195 | exc_register(EXC_TLBL, "tlbinvl", (iroutine) tlbinv_exception);
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| 196 | exc_register(EXC_TLBS, "tlbinvl", (iroutine) tlbinv_exception);
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| 197 | exc_register(EXC_Int, "interrupt", (iroutine) interrupt_exception);
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[7a8c866a] | 198 | #ifdef CONFIG_FPU_LAZY
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[49a39c2] | 199 | exc_register(EXC_CpU, "cpunus", (iroutine) cpuns_exception);
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[7a8c866a] | 200 | #endif
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[49a39c2] | 201 | exc_register(EXC_Sys, "syscall", (iroutine) syscall_exception);
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[7a8c866a] | 202 | }
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