source: mainline/arch/mips32/src/asm.S@ 3b712407

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3b712407 was 1b109cb, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

Cleanup of mips

  • inline register reads
  • better fpu disable/enable - global settings is automatically propagated to task
  • fast syscall
  • Property mode set to 100644
File size: 4.8 KB
Line 
1#
2# Copyright (C) 2003-2004 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29#include <arch/asm/regname.h>
30
31.text
32
33.macro cp0_read reg
34 mfc0 $2,\reg
35 j $31
36 nop
37.endm
38
39.macro cp0_write reg
40 mtc0 $4,\reg
41 j $31
42 nop
43.endm
44
45.set noat
46.set noreorder
47.set nomacro
48
49.global cpu_halt
50cpu_halt:
51 j cpu_halt
52 nop
53
54
55.global memsetb
56memsetb:
57 j _memsetb
58 nop
59
60.global memcpy
61memcpy:
62 j _memcpy
63 nop
64
65.macro fpu_gp_save reg ctx
66 mfc1 $t0,$\reg
67 sw $t0, \reg*4(\ctx)
68.endm
69
70.macro fpu_gp_restore reg ctx
71 lw $t0, \reg*4(\ctx)
72 mtc1 $t0,$\reg
73.endm
74
75.macro fpu_ct_save reg ctx
76 cfc1 $t0,$1
77 sw $t0, (\reg+32)*4(\ctx)
78.endm
79
80.macro fpu_ct_restore reg ctx
81 lw $t0, (\reg+32)*4(\ctx)
82 ctc1 $t0,$\reg
83.endm
84
85
86.global fpu_context_save
87fpu_context_save:
88#ifdef ARCH_HAS_FPU
89 fpu_gp_save 0,$a0
90 fpu_gp_save 1,$a0
91 fpu_gp_save 2,$a0
92 fpu_gp_save 3,$a0
93 fpu_gp_save 4,$a0
94 fpu_gp_save 5,$a0
95 fpu_gp_save 6,$a0
96 fpu_gp_save 7,$a0
97 fpu_gp_save 8,$a0
98 fpu_gp_save 9,$a0
99 fpu_gp_save 10,$a0
100 fpu_gp_save 11,$a0
101 fpu_gp_save 12,$a0
102 fpu_gp_save 13,$a0
103 fpu_gp_save 14,$a0
104 fpu_gp_save 15,$a0
105 fpu_gp_save 16,$a0
106 fpu_gp_save 17,$a0
107 fpu_gp_save 18,$a0
108 fpu_gp_save 19,$a0
109 fpu_gp_save 20,$a0
110 fpu_gp_save 21,$a0
111 fpu_gp_save 22,$a0
112 fpu_gp_save 23,$a0
113 fpu_gp_save 24,$a0
114 fpu_gp_save 25,$a0
115 fpu_gp_save 26,$a0
116 fpu_gp_save 27,$a0
117 fpu_gp_save 28,$a0
118 fpu_gp_save 29,$a0
119 fpu_gp_save 30,$a0
120 fpu_gp_save 31,$a0
121
122 fpu_ct_save 1,$a0
123 fpu_ct_save 2,$a0
124 fpu_ct_save 3,$a0
125 fpu_ct_save 4,$a0
126 fpu_ct_save 5,$a0
127 fpu_ct_save 6,$a0
128 fpu_ct_save 7,$a0
129 fpu_ct_save 8,$a0
130 fpu_ct_save 9,$a0
131 fpu_ct_save 10,$a0
132 fpu_ct_save 11,$a0
133 fpu_ct_save 12,$a0
134 fpu_ct_save 13,$a0
135 fpu_ct_save 14,$a0
136 fpu_ct_save 15,$a0
137 fpu_ct_save 16,$a0
138 fpu_ct_save 17,$a0
139 fpu_ct_save 18,$a0
140 fpu_ct_save 19,$a0
141 fpu_ct_save 20,$a0
142 fpu_ct_save 21,$a0
143 fpu_ct_save 22,$a0
144 fpu_ct_save 23,$a0
145 fpu_ct_save 24,$a0
146 fpu_ct_save 25,$a0
147 fpu_ct_save 26,$a0
148 fpu_ct_save 27,$a0
149 fpu_ct_save 28,$a0
150 fpu_ct_save 29,$a0
151 fpu_ct_save 30,$a0
152 fpu_ct_save 31,$a0
153#endif
154 j $ra
155 nop
156
157.global fpu_context_restore
158fpu_context_restore:
159#ifdef ARCH_HAS_FPU
160 fpu_gp_restore 0,$a0
161 fpu_gp_restore 1,$a0
162 fpu_gp_restore 2,$a0
163 fpu_gp_restore 3,$a0
164 fpu_gp_restore 4,$a0
165 fpu_gp_restore 5,$a0
166 fpu_gp_restore 6,$a0
167 fpu_gp_restore 7,$a0
168 fpu_gp_restore 8,$a0
169 fpu_gp_restore 9,$a0
170 fpu_gp_restore 10,$a0
171 fpu_gp_restore 11,$a0
172 fpu_gp_restore 12,$a0
173 fpu_gp_restore 13,$a0
174 fpu_gp_restore 14,$a0
175 fpu_gp_restore 15,$a0
176 fpu_gp_restore 16,$a0
177 fpu_gp_restore 17,$a0
178 fpu_gp_restore 18,$a0
179 fpu_gp_restore 19,$a0
180 fpu_gp_restore 20,$a0
181 fpu_gp_restore 21,$a0
182 fpu_gp_restore 22,$a0
183 fpu_gp_restore 23,$a0
184 fpu_gp_restore 24,$a0
185 fpu_gp_restore 25,$a0
186 fpu_gp_restore 26,$a0
187 fpu_gp_restore 27,$a0
188 fpu_gp_restore 28,$a0
189 fpu_gp_restore 29,$a0
190 fpu_gp_restore 30,$a0
191 fpu_gp_restore 31,$a0
192
193 fpu_ct_restore 1,$a0
194 fpu_ct_restore 2,$a0
195 fpu_ct_restore 3,$a0
196 fpu_ct_restore 4,$a0
197 fpu_ct_restore 5,$a0
198 fpu_ct_restore 6,$a0
199 fpu_ct_restore 7,$a0
200 fpu_ct_restore 8,$a0
201 fpu_ct_restore 9,$a0
202 fpu_ct_restore 10,$a0
203 fpu_ct_restore 11,$a0
204 fpu_ct_restore 12,$a0
205 fpu_ct_restore 13,$a0
206 fpu_ct_restore 14,$a0
207 fpu_ct_restore 15,$a0
208 fpu_ct_restore 16,$a0
209 fpu_ct_restore 17,$a0
210 fpu_ct_restore 18,$a0
211 fpu_ct_restore 19,$a0
212 fpu_ct_restore 20,$a0
213 fpu_ct_restore 21,$a0
214 fpu_ct_restore 22,$a0
215 fpu_ct_restore 23,$a0
216 fpu_ct_restore 24,$a0
217 fpu_ct_restore 25,$a0
218 fpu_ct_restore 26,$a0
219 fpu_ct_restore 27,$a0
220 fpu_ct_restore 28,$a0
221 fpu_ct_restore 29,$a0
222 fpu_ct_restore 30,$a0
223 fpu_ct_restore 31,$a0
224#endif
225 j $ra
226 nop
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