source: mainline/arch/mips32/include/mm/tlb.h@ 052da81

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 052da81 was 052da81, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

Fixes in memory allocator

  • proper kernel blacklisting, when kernel not loaded on page boundary
  • correct zone adding in zone list (how could this work??)
  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 * Copyright (C) 2003-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __mips32_TLB_H__
30#define __mips32_TLB_H__
31
32#include <arch/exception.h>
33#include <typedefs.h>
34
35#ifdef TLBCNT
36# define TLB_ENTRY_COUNT TLBCNT
37#else
38# define TLB_ENTRY_COUNT 48
39#endif
40
41#define TLB_WIRED 1
42#define TLB_KSTACK_WIRED_INDEX 0
43
44#define TLB_PAGE_MASK_16K (0x3<<13)
45
46#define PAGE_UNCACHED 2
47#define PAGE_CACHEABLE_EXC_WRITE 5
48
49typedef union entry_lo entry_lo_t;
50typedef union entry_hi entry_hi_t;
51typedef union page_mask page_mask_t;
52typedef union index tlb_index_t;
53
54union entry_lo {
55 struct {
56#ifdef BIG_ENDIAN
57 unsigned : 2; /* zero */
58 unsigned pfn : 24; /* frame number */
59 unsigned c : 3; /* cache coherency attribute */
60 unsigned d : 1; /* dirty/write-protect bit */
61 unsigned v : 1; /* valid bit */
62 unsigned g : 1; /* global bit */
63#else
64 unsigned g : 1; /* global bit */
65 unsigned v : 1; /* valid bit */
66 unsigned d : 1; /* dirty/write-protect bit */
67 unsigned c : 3; /* cache coherency attribute */
68 unsigned pfn : 24; /* frame number */
69 unsigned : 2; /* zero */
70#endif
71 } __attribute__ ((packed));
72 __u32 value;
73};
74
75/** Page Table Entry. */
76struct pte {
77 unsigned g : 1; /**< Global bit. */
78 unsigned p : 1; /**< Present bit. */
79 unsigned d : 1; /**< Dirty bit. */
80 unsigned cacheable : 1; /**< Cacheable bit. */
81 unsigned : 1; /**< Unused. */
82 unsigned soft_valid : 1; /**< Valid content even if not present. */
83 unsigned pfn : 24; /**< Physical frame number. */
84 unsigned w : 1; /**< Page writable bit. */
85 unsigned a : 1; /**< Accessed bit. */
86};
87
88union entry_hi {
89 struct {
90#ifdef BIG_ENDIAN
91 unsigned vpn2 : 19;
92 unsigned : 5;
93 unsigned asid : 8;
94#else
95 unsigned asid : 8;
96 unsigned : 5;
97 unsigned vpn2 : 19;
98#endif
99 } __attribute__ ((packed));
100 __u32 value;
101};
102
103union page_mask {
104 struct {
105#ifdef BIG_ENDIAN
106 unsigned : 7;
107 unsigned mask : 12;
108 unsigned : 13;
109#else
110 unsigned : 13;
111 unsigned mask : 12;
112 unsigned : 7;
113#endif
114 } __attribute__ ((packed));
115 __u32 value;
116};
117
118union index {
119 struct {
120#ifdef BIG_ENDIAN
121 unsigned p : 1;
122 unsigned : 27;
123 unsigned index : 4;
124#else
125 unsigned index : 4;
126 unsigned : 27;
127 unsigned p : 1;
128#endif
129 } __attribute__ ((packed));
130 __u32 value;
131};
132
133/** Probe TLB for Matching Entry
134 *
135 * Probe TLB for Matching Entry.
136 */
137static inline void tlbp(void)
138{
139 __asm__ volatile ("tlbp\n\t");
140}
141
142
143/** Read Indexed TLB Entry
144 *
145 * Read Indexed TLB Entry.
146 */
147static inline void tlbr(void)
148{
149 __asm__ volatile ("tlbr\n\t");
150}
151
152/** Write Indexed TLB Entry
153 *
154 * Write Indexed TLB Entry.
155 */
156static inline void tlbwi(void)
157{
158 __asm__ volatile ("tlbwi\n\t");
159}
160
161/** Write Random TLB Entry
162 *
163 * Write Random TLB Entry.
164 */
165static inline void tlbwr(void)
166{
167 __asm__ volatile ("tlbwr\n\t");
168}
169
170#define tlb_invalidate(asid) tlb_invalidate_asid(asid)
171
172extern void tlb_invalid(struct exception_regdump *pstate);
173extern void tlb_refill(struct exception_regdump *pstate);
174extern void tlb_modified(struct exception_regdump *pstate);
175
176#endif
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