source: mainline/arch/mips32/include/atomic.h@ b524c5e0

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b524c5e0 was 10c071e, checked in by Jakub Jermar <jakub@…>, 20 years ago

Fix ia64 and sparc64 to compile with new atomic_t.
Fix rwlock test #5 and semaphore test #1 to compile with new atomic_t.

sparc64 work.
TBA must be set before a function call when MMU is switched off.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 * Copyright (C) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __mips32_ATOMIC_H__
30#define __mips32_ATOMIC_H__
31
32#include <arch/types.h>
33
34#define atomic_inc(x) ((void) atomic_add(x, 1))
35#define atomic_dec(x) ((void) atomic_add(x, -1))
36
37#define atomic_inc_pre(x) (atomic_add(x, 1) - 1)
38#define atomic_dec_pre(x) (atomic_add(x, -1) + 1)
39
40#define atomic_inc_post(x) atomic_add(x, 1)
41#define atomic_dec_post(x) atomic_add(x, -1)
42
43
44typedef struct { volatile __u32 count; } atomic_t;
45
46/* Atomic addition of immediate value.
47 *
48 * @param val Memory location to which will be the immediate value added.
49 * @param i Signed immediate that will be added to *val.
50 *
51 * @return Value after addition.
52 */
53static inline count_t atomic_add(atomic_t *val, int i)
54{
55 count_t tmp, v;
56
57 __asm__ volatile (
58 "1:\n"
59 " ll %0, %1\n"
60 " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */
61 " move %2, %0\n"
62 " sc %0, %1\n"
63 " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
64 /* nop */ /* nop is inserted automatically by compiler */
65 : "=r" (tmp), "=m" (val->count), "=r" (v)
66 : "i" (i), "i" (0)
67 );
68
69 return v;
70}
71
72/* Reads/writes are atomic on mips for 4-bytes */
73
74static inline void atomic_set(atomic_t *val, __u32 i)
75{
76 val->count = i;
77}
78
79static inline __u32 atomic_get(atomic_t *val)
80{
81 return val->count;
82}
83
84#endif
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