source: mainline/arch/mips32/_link.ld.in@ f5df72d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f5df72d was 6e259d5, checked in by Martin Decky <martin@…>, 20 years ago

link kernel in ARCH's native format first, then use objcopy to create output format

  • Property mode set to 100644
File size: 1.0 KB
RevLine 
[f761f1eb]1/*
[2a99fa8]2 * MIPS32 linker script
[f761f1eb]3 *
4 * kernel text
5 * kernel data
6 *
7 */
[ffc277e]8#undef mips
9#define mips mips
[f761f1eb]10
[ffc277e]11OUTPUT_ARCH(mips)
[38de8a5]12
[e3f41b6]13ENTRY(kernel_image_start)
[f761f1eb]14
15SECTIONS {
[24241cf]16 . = KERNEL_LOAD_ADDRESS;
[ffc277e]17 .text : {
[ac5d02b]18 ktext_start = .;
19 *(.text);
20 ktext_end = .;
[ffc277e]21 }
22 .data : {
[ac5d02b]23 kdata_start = .;
24 *(.data); /* initialized data */
[c832cc0a]25 hardcoded_ktext_size = .;
26 LONG(ktext_end - ktext_start);
27 hardcoded_kdata_size = .;
28 LONG(kdata_end - kdata_start);
29 hardcoded_load_address = .;
[24241cf]30 LONG(KERNEL_LOAD_ADDRESS);
31 *(.rodata*);
32 *(.sdata);
33 *(.reginfo);
[3156582]34 /* Unfortunately IRIX does not allow us
35 * to include this as a last section :-(
36 * BSS/SBSS addresses will be wrong */
37 symbol_table = .;
38 *(symtab.*);
[ffc277e]39 }
40 _gp = . + 0x8000;
41 .lit8 : { *(.lit8) }
42 .lit4 : { *(.lit4) }
43 .sbss : {
44 *(.sbss);
[ac5d02b]45 *(.scommon);
[ffc277e]46 }
47 .bss : {
48 *(.bss); /* uninitialized static variables */
[ac5d02b]49 *(COMMON); /* global variables */
[ffc277e]50 }
[24241cf]51
[ffc277e]52 kdata_end = .;
53
[24241cf]54 /DISCARD/ : {
55 *(.mdebug*);
56 *(.pdr);
57 *(.comment);
58 *(.note);
59 }
[f761f1eb]60}
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