source: mainline/arch/mips32/Makefile.inc@ f275cb3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since f275cb3 was 6d7ffa65, checked in by Jakub Jermar <jakub@…>, 20 years ago

Memory management work.
Move generic 4-level page table interface to genarch
and enable architectures to use different virtual memory
mechanisms (e.g. page hash tables).
Start page hash table support.
Switch ia64 and sparc64 to page hash tables.
Other architectures keep on using 4-level page table interface.

  • Property mode set to 100644
File size: 3.7 KB
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1#
2# Copyright (C) 2005 Martin Decky
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29## Toolchain configuration
30#
31
32BFD_ARCH = mips
33TARGET = mipsel-linux-gnu
34TOOLCHAIN_DIR = /usr/local/mipsel/bin
35
36## Make some default assumptions
37#
38
39ifndef MIPS_MACHINE
40 MIPS_MACHINE = msim
41endif
42
43KERNEL_LOAD_ADDRESS = 0x80100000
44INIT_ADDRESS = 0x80110000
45INIT_SIZE = 65536
46CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss
47DEFS += -DMACHINE=${MIPS_MACHINE} -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS} -DINIT_ADDRESS=${INIT_ADDRESS} -DINIT_SIZE=${INIT_SIZE}
48
49## Compile with hierarchical page tables support.
50#
51
52CONFIG_PAGE_PT = y
53
54
55## Accepted MACHINEs
56#
57
58ifeq ($(MIPS_MACHINE),indy)
59 # GCC 4.0.1 compiled for mipsEL has problems compiling in
60 # BigEndian mode with the swl/swr/lwl/lwr instructions.
61 # We have to compile it with mips-sgi-irix5 to get it right.
62
63 BFD_NAME = elf32-bigmips
64 BFD = ecoff-bigmips --impure
65 TARGET = mips-sgi-irix5
66 TOOLCHAIN_DIR = /usr/local/mips/bin
67 KERNEL_LOAD_ADDRESS = 0x88002000
68 CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -march=r4600
69endif
70ifeq ($(MIPS_MACHINE),lgxemul)
71 BFD_NAME=elf32-tradlittlemips
72 BFD = ecoff-littlemips
73 CFLAGS += -DHAVE_FPU -mips3
74endif
75ifeq ($(MIPS_MACHINE),bgxemul)
76 BFD_NAME=elf32-bigmips
77 BFD = ecoff-bigmips
78 TARGET = mips-sgi-irix5
79 TOOLCHAIN_DIR = /usr/local/mips/bin
80 CFLAGS += -EB -DBIG_ENDIAN -DHAVE_FPU -mips3
81endif
82ifeq ($(MIPS_MACHINE),simics)
83 # SIMICS 4kc emulation is broken, although for instructions
84 # that do not bother us
85
86 BFD_NAME = elf32-tradlittlemips
87 BFD = elf32-tradlittlemips
88 CFLAGS += -mhard-float -mips3 -DTLBCNT=16
89 TLBCNT = 16
90endif
91ifeq ($(MIPS_MACHINE),msim)
92 BFD_NAME = elf32-tradlittlemips
93 BFD = binary
94 CFLAGS += -mhard-float -mips3
95endif
96
97
98ARCH_SOURCES = \
99 arch/$(ARCH)/src/start.S \
100 arch/$(ARCH)/src/context.S \
101 arch/$(ARCH)/src/panic.S \
102 arch/$(ARCH)/src/mips32.c \
103 arch/$(ARCH)/src/dummy.S \
104 arch/$(ARCH)/src/console.c \
105 arch/$(ARCH)/src/asm.S \
106 arch/$(ARCH)/src/exception.c \
107 arch/$(ARCH)/src/interrupt.c \
108 arch/$(ARCH)/src/cache.c \
109 arch/$(ARCH)/src/debugger.c \
110 arch/$(ARCH)/src/cpu/cpu.c \
111 arch/$(ARCH)/src/mm/asid.c \
112 arch/$(ARCH)/src/mm/frame.c \
113 arch/$(ARCH)/src/mm/page.c \
114 arch/$(ARCH)/src/mm/tlb.c \
115 arch/$(ARCH)/src/mm/vm.c \
116 arch/$(ARCH)/src/fpu_context.c \
117 arch/$(ARCH)/src/drivers/arc.c \
118 arch/$(ARCH)/src/drivers/msim.c \
119 arch/$(ARCH)/src/drivers/serial.c
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