source: mainline/arch/mips/src/start.S@ 85ddc05

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 85ddc05 was 85ddc05, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Bad stack settings. Why did not msim complain??

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File size: 5.0 KB
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[a5d1331]1#
[178ec7b]2# Copyright (C) 2003-2004 Jakub Jermar
[f761f1eb]3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
[e84439a]29#define __ASM__
30
31#include <arch/asm/regname.h>
32#include <arch/mm/page.h>
33#include <arch/asm/boot.h>
[909c6e3]34#include <arch/context_offset.h>
[e84439a]35
[f761f1eb]36.text
37
38.set noat
39.set noreorder
40.set nomacro
41
42.global kernel_image_start
43.global tlb_refill_entry
44.global cache_error_entry
45.global exception_entry
[2bd4fdf]46.global userspace_asm
[f761f1eb]47
[2bd4fdf]48# Save registers to space defined by \r
49# We will change $at on the way
[e84439a]50.macro REGISTERS_STORE r
51 sw $at,EOFFSET_AT(\r)
52 sw $v0,EOFFSET_V0(\r)
53 sw $v1,EOFFSET_V1(\r)
54 sw $a0,EOFFSET_A0(\r)
55 sw $a1,EOFFSET_A1(\r)
56 sw $a2,EOFFSET_A2(\r)
57 sw $a3,EOFFSET_A3(\r)
[909c6e3]58 sw $t0,EOFFSET_T0(\r)
[e84439a]59 sw $t1,EOFFSET_T1(\r)
60 sw $t2,EOFFSET_T2(\r)
61 sw $t3,EOFFSET_T3(\r)
62 sw $t4,EOFFSET_T4(\r)
63 sw $t5,EOFFSET_T5(\r)
64 sw $t6,EOFFSET_T6(\r)
65 sw $t7,EOFFSET_T7(\r)
66 sw $t8,EOFFSET_T8(\r)
67 sw $t9,EOFFSET_T9(\r)
[2bd4fdf]68
69 mflo $at
70 sw $at, EOFFSET_LO(\r)
71 mfhi $at
72 sw $at, EOFFSET_HI(\r)
73
[e84439a]74 sw $s0,EOFFSET_S0(\r)
75 sw $s1,EOFFSET_S1(\r)
76 sw $s2,EOFFSET_S2(\r)
77 sw $s3,EOFFSET_S3(\r)
78 sw $s4,EOFFSET_S4(\r)
79 sw $s5,EOFFSET_S5(\r)
80 sw $s6,EOFFSET_S6(\r)
81 sw $s7,EOFFSET_S7(\r)
82 sw $s8,EOFFSET_S8(\r)
83 sw $gp,EOFFSET_GP(\r)
84 sw $ra,EOFFSET_RA(\r)
[2bd4fdf]85 sw $sp,EOFFSET_SP(\r)
86
87 mfc0 $at, $status
88 sw $at,EOFFSET_STATUS(\r)
[909c6e3]89 mfc0 $at, $epc
90 sw $at,EOFFSET_EPC(\r)
[e84439a]91.endm
92
93.macro REGISTERS_LOAD r
94 lw $v0,EOFFSET_V0(\r)
95 lw $v1,EOFFSET_V1(\r)
96 lw $a0,EOFFSET_A0(\r)
97 lw $a1,EOFFSET_A1(\r)
98 lw $a2,EOFFSET_A2(\r)
99 lw $a3,EOFFSET_A3(\r)
[909c6e3]100 lw $t0,EOFFSET_T0(\r)
[e84439a]101 lw $t1,EOFFSET_T1(\r)
102 lw $t2,EOFFSET_T2(\r)
103 lw $t3,EOFFSET_T3(\r)
104 lw $t4,EOFFSET_T4(\r)
105 lw $t5,EOFFSET_T5(\r)
106 lw $t6,EOFFSET_T6(\r)
107 lw $t7,EOFFSET_T7(\r)
108 lw $t8,EOFFSET_T8(\r)
109 lw $t9,EOFFSET_T9(\r)
110 lw $s0,EOFFSET_S0(\r)
111 lw $s1,EOFFSET_S1(\r)
112 lw $s2,EOFFSET_S2(\r)
113 lw $s3,EOFFSET_S3(\r)
114 lw $s4,EOFFSET_S4(\r)
115 lw $s5,EOFFSET_S5(\r)
116 lw $s6,EOFFSET_S6(\r)
117 lw $s7,EOFFSET_S7(\r)
118 lw $s8,EOFFSET_S8(\r)
119 lw $gp,EOFFSET_GP(\r)
120 lw $ra,EOFFSET_RA(\r)
121
[2bd4fdf]122 lw $at,EOFFSET_LO(\r)
123 mtlo $at
124 lw $at,EOFFSET_HI(\r)
125 mthi $at
126
127 lw $at,EOFFSET_STATUS(\r)
128 mtc0 $at, $status
[909c6e3]129 lw $at,EOFFSET_EPC(\r)
130 mtc0 $at, $epc
[2bd4fdf]131
132 lw $at,EOFFSET_AT(\r)
133 lw $sp,EOFFSET_SP(\r)
[e84439a]134.endm
135
[2bd4fdf]136# Move kernel stack pointer address to register K0
137# - if we are in user mode, load the appropriate stack
138# address
139.macro KERNEL_STACK_TO_K0
140 # If we are in user mode
141 mfc0 $k0, $status
142 andi $k0, 0x10
143
144 beq $k0, $0, 1f
145 add $k0, $sp, 0
[e84439a]146
[2bd4fdf]147 # Move $k0 pointer to kernel stack
148 lui $k0, %hi(supervisor_sp)
[85ddc05]149 ori $k0, $k0, %lo(supervisor_sp)
[2bd4fdf]150 # Move $k0 (superveisor_sp)
151 lw $k0, 0($k0)
1521:
153.endm
154
[f761f1eb]155.org 0x0
156tlb_refill_entry:
[4e1d008]157 j tlb_refill_handler
158 nop
[f761f1eb]159
160.org 0x100
161cache_error_entry:
[4e1d008]162 j cache_error_handler
163 nop
[76cec1e]164
[f761f1eb]165.org 0x180
[2bd4fdf]166norm_exception:
167 j exception_handler
168 nop
[76cec1e]169
[2bd4fdf]170.org 0x200
171iv_exception:
172 j exception_handler
173 nop
[76cec1e]174
[2bd4fdf]175.org KA2PA(KERNEL_STARTUP_ADDRESS)
[e84439a]176kernel_image_start:
177 /* Load temporary stack */
[2bd4fdf]178 lui $sp, %hi(end_stack)
[85ddc05]179 ori $sp, $sp, %lo(end_stack)
[e84439a]180
181 /* Not sure about this, but might be needed for PIC code???? */
182 lui $gp, 0x8000
183
184 jal main_bsp
185 nop
186
[2bd4fdf]187
[e84439a]188 .space TEMP_STACK_SIZE
[2bd4fdf]189end_stack:
190
191exception_handler:
192exception_entry:
193 KERNEL_STACK_TO_K0
194 sub $k0, REGISTER_SPACE
195 REGISTERS_STORE $k0
196 add $sp, $k0, 0
197
[909c6e3]198 add $a0, $sp, 0
199 jal exception /* exception(register_space) */
[2bd4fdf]200 nop
201
202 REGISTERS_LOAD $sp
203 # The $sp is automatically restored to former value
204 eret
205 nop
[e84439a]206
[f761f1eb]207tlb_refill_handler:
[2bd4fdf]208 KERNEL_STACK_TO_K0
209 sub $k0, REGISTER_SPACE
210 REGISTERS_STORE $k0
211 add $sp, $k0, 0
[76cec1e]212
[909c6e3]213 add $a0, $sp, 0
214 jal tlb_refill /* tlb_refill(register_space) */
[4e1d008]215 nop
[76cec1e]216
[e84439a]217 REGISTERS_LOAD $sp
[76cec1e]218
[4e1d008]219 eret
[e84439a]220 nop
[f761f1eb]221
222cache_error_handler:
[2bd4fdf]223 KERNEL_STACK_TO_K0
[e84439a]224 sub $sp, REGISTER_SPACE
225 REGISTERS_STORE $sp
[2bd4fdf]226 add $sp, $k0, 0
[f761f1eb]227
[4e1d008]228 jal cache_error
229 nop
[76cec1e]230
[e84439a]231 REGISTERS_LOAD $sp
[f761f1eb]232
[4e1d008]233 eret
[a5d1331]234 nop
[2bd4fdf]235
236userspace_asm:
237 add $sp, $a0, 0
238 eret
239 nop
240
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