[a5d1331] | 1 | #
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[178ec7b] | 2 | # Copyright (C) 2003-2004 Jakub Jermar
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[f761f1eb] | 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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[e84439a] | 29 | #define __ASM__
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| 30 |
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| 31 | #include <arch/asm/regname.h>
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| 32 | #include <arch/mm/page.h>
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| 33 | #include <arch/asm/boot.h>
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[909c6e3] | 34 | #include <arch/context_offset.h>
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[e84439a] | 35 |
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[f761f1eb] | 36 | .text
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| 37 |
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| 38 | .set noat
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| 39 | .set noreorder
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| 40 | .set nomacro
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| 41 |
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| 42 | .global kernel_image_start
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| 43 | .global tlb_refill_entry
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| 44 | .global cache_error_entry
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| 45 | .global exception_entry
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[2bd4fdf] | 46 | .global userspace_asm
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[f761f1eb] | 47 |
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[2bd4fdf] | 48 | # Save registers to space defined by \r
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| 49 | # We will change $at on the way
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[e84439a] | 50 | .macro REGISTERS_STORE r
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| 51 | sw $at,EOFFSET_AT(\r)
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| 52 | sw $v0,EOFFSET_V0(\r)
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| 53 | sw $v1,EOFFSET_V1(\r)
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| 54 | sw $a0,EOFFSET_A0(\r)
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| 55 | sw $a1,EOFFSET_A1(\r)
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| 56 | sw $a2,EOFFSET_A2(\r)
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| 57 | sw $a3,EOFFSET_A3(\r)
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[909c6e3] | 58 | sw $t0,EOFFSET_T0(\r)
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[e84439a] | 59 | sw $t1,EOFFSET_T1(\r)
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| 60 | sw $t2,EOFFSET_T2(\r)
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| 61 | sw $t3,EOFFSET_T3(\r)
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| 62 | sw $t4,EOFFSET_T4(\r)
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| 63 | sw $t5,EOFFSET_T5(\r)
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| 64 | sw $t6,EOFFSET_T6(\r)
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| 65 | sw $t7,EOFFSET_T7(\r)
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| 66 | sw $t8,EOFFSET_T8(\r)
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| 67 | sw $t9,EOFFSET_T9(\r)
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[2bd4fdf] | 68 |
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| 69 | mflo $at
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| 70 | sw $at, EOFFSET_LO(\r)
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| 71 | mfhi $at
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| 72 | sw $at, EOFFSET_HI(\r)
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| 73 |
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[e84439a] | 74 | sw $s0,EOFFSET_S0(\r)
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| 75 | sw $s1,EOFFSET_S1(\r)
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| 76 | sw $s2,EOFFSET_S2(\r)
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| 77 | sw $s3,EOFFSET_S3(\r)
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| 78 | sw $s4,EOFFSET_S4(\r)
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| 79 | sw $s5,EOFFSET_S5(\r)
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| 80 | sw $s6,EOFFSET_S6(\r)
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| 81 | sw $s7,EOFFSET_S7(\r)
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| 82 | sw $s8,EOFFSET_S8(\r)
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| 83 | sw $gp,EOFFSET_GP(\r)
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| 84 | sw $ra,EOFFSET_RA(\r)
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[2bd4fdf] | 85 | sw $sp,EOFFSET_SP(\r)
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| 86 |
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| 87 | mfc0 $at, $status
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| 88 | sw $at,EOFFSET_STATUS(\r)
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[909c6e3] | 89 | mfc0 $at, $epc
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| 90 | sw $at,EOFFSET_EPC(\r)
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[e84439a] | 91 | .endm
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| 92 |
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| 93 | .macro REGISTERS_LOAD r
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| 94 | lw $v0,EOFFSET_V0(\r)
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| 95 | lw $v1,EOFFSET_V1(\r)
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| 96 | lw $a0,EOFFSET_A0(\r)
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| 97 | lw $a1,EOFFSET_A1(\r)
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| 98 | lw $a2,EOFFSET_A2(\r)
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| 99 | lw $a3,EOFFSET_A3(\r)
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[909c6e3] | 100 | lw $t0,EOFFSET_T0(\r)
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[e84439a] | 101 | lw $t1,EOFFSET_T1(\r)
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| 102 | lw $t2,EOFFSET_T2(\r)
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| 103 | lw $t3,EOFFSET_T3(\r)
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| 104 | lw $t4,EOFFSET_T4(\r)
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| 105 | lw $t5,EOFFSET_T5(\r)
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| 106 | lw $t6,EOFFSET_T6(\r)
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| 107 | lw $t7,EOFFSET_T7(\r)
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| 108 | lw $t8,EOFFSET_T8(\r)
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| 109 | lw $t9,EOFFSET_T9(\r)
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| 110 | lw $s0,EOFFSET_S0(\r)
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| 111 | lw $s1,EOFFSET_S1(\r)
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| 112 | lw $s2,EOFFSET_S2(\r)
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| 113 | lw $s3,EOFFSET_S3(\r)
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| 114 | lw $s4,EOFFSET_S4(\r)
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| 115 | lw $s5,EOFFSET_S5(\r)
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| 116 | lw $s6,EOFFSET_S6(\r)
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| 117 | lw $s7,EOFFSET_S7(\r)
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| 118 | lw $s8,EOFFSET_S8(\r)
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| 119 | lw $gp,EOFFSET_GP(\r)
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| 120 | lw $ra,EOFFSET_RA(\r)
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| 121 |
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[2bd4fdf] | 122 | lw $at,EOFFSET_LO(\r)
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| 123 | mtlo $at
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| 124 | lw $at,EOFFSET_HI(\r)
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| 125 | mthi $at
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| 126 |
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| 127 | lw $at,EOFFSET_STATUS(\r)
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| 128 | mtc0 $at, $status
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[909c6e3] | 129 | lw $at,EOFFSET_EPC(\r)
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| 130 | mtc0 $at, $epc
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[2bd4fdf] | 131 |
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| 132 | lw $at,EOFFSET_AT(\r)
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| 133 | lw $sp,EOFFSET_SP(\r)
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[e84439a] | 134 | .endm
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| 135 |
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[2bd4fdf] | 136 | # Move kernel stack pointer address to register K0
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| 137 | # - if we are in user mode, load the appropriate stack
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| 138 | # address
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| 139 | .macro KERNEL_STACK_TO_K0
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| 140 | # If we are in user mode
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| 141 | mfc0 $k0, $status
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| 142 | andi $k0, 0x10
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| 143 |
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| 144 | beq $k0, $0, 1f
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| 145 | add $k0, $sp, 0
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[e84439a] | 146 |
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[2bd4fdf] | 147 | # Move $k0 pointer to kernel stack
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| 148 | lui $k0, %hi(supervisor_sp)
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[85ddc05] | 149 | ori $k0, $k0, %lo(supervisor_sp)
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[2bd4fdf] | 150 | # Move $k0 (superveisor_sp)
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| 151 | lw $k0, 0($k0)
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| 152 | 1:
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| 153 | .endm
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| 154 |
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[f761f1eb] | 155 | .org 0x0
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| 156 | tlb_refill_entry:
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[4e1d008] | 157 | j tlb_refill_handler
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| 158 | nop
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[f761f1eb] | 159 |
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| 160 | .org 0x100
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| 161 | cache_error_entry:
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[4e1d008] | 162 | j cache_error_handler
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| 163 | nop
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[76cec1e] | 164 |
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[f761f1eb] | 165 | .org 0x180
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[2bd4fdf] | 166 | norm_exception:
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| 167 | j exception_handler
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| 168 | nop
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[76cec1e] | 169 |
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[2bd4fdf] | 170 | .org 0x200
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| 171 | iv_exception:
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| 172 | j exception_handler
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| 173 | nop
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[76cec1e] | 174 |
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[2bd4fdf] | 175 | .org KA2PA(KERNEL_STARTUP_ADDRESS)
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[e84439a] | 176 | kernel_image_start:
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| 177 | /* Load temporary stack */
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[2bd4fdf] | 178 | lui $sp, %hi(end_stack)
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[85ddc05] | 179 | ori $sp, $sp, %lo(end_stack)
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[e84439a] | 180 |
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| 181 | /* Not sure about this, but might be needed for PIC code???? */
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| 182 | lui $gp, 0x8000
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| 183 |
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| 184 | jal main_bsp
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| 185 | nop
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| 186 |
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[2bd4fdf] | 187 |
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[e84439a] | 188 | .space TEMP_STACK_SIZE
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[2bd4fdf] | 189 | end_stack:
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| 190 |
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| 191 | exception_handler:
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| 192 | exception_entry:
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| 193 | KERNEL_STACK_TO_K0
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| 194 | sub $k0, REGISTER_SPACE
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| 195 | REGISTERS_STORE $k0
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| 196 | add $sp, $k0, 0
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| 197 |
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[909c6e3] | 198 | add $a0, $sp, 0
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| 199 | jal exception /* exception(register_space) */
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[2bd4fdf] | 200 | nop
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| 201 |
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| 202 | REGISTERS_LOAD $sp
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| 203 | # The $sp is automatically restored to former value
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| 204 | eret
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| 205 | nop
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[e84439a] | 206 |
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[f761f1eb] | 207 | tlb_refill_handler:
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[2bd4fdf] | 208 | KERNEL_STACK_TO_K0
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| 209 | sub $k0, REGISTER_SPACE
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| 210 | REGISTERS_STORE $k0
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| 211 | add $sp, $k0, 0
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[76cec1e] | 212 |
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[909c6e3] | 213 | add $a0, $sp, 0
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| 214 | jal tlb_refill /* tlb_refill(register_space) */
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[4e1d008] | 215 | nop
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[76cec1e] | 216 |
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[e84439a] | 217 | REGISTERS_LOAD $sp
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[76cec1e] | 218 |
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[4e1d008] | 219 | eret
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[e84439a] | 220 | nop
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[f761f1eb] | 221 |
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| 222 | cache_error_handler:
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[2bd4fdf] | 223 | KERNEL_STACK_TO_K0
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[e84439a] | 224 | sub $sp, REGISTER_SPACE
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| 225 | REGISTERS_STORE $sp
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[2bd4fdf] | 226 | add $sp, $k0, 0
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[f761f1eb] | 227 |
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[4e1d008] | 228 | jal cache_error
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| 229 | nop
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[76cec1e] | 230 |
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[e84439a] | 231 | REGISTERS_LOAD $sp
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[f761f1eb] | 232 |
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[4e1d008] | 233 | eret
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[a5d1331] | 234 | nop
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[2bd4fdf] | 235 |
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| 236 | userspace_asm:
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| 237 | add $sp, $a0, 0
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| 238 | eret
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| 239 | nop
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| 240 |
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