source: mainline/arch/mips/include/mm/tlb.h@ 568337b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 568337b was a1a03f9, checked in by Jakub Jermar <jakub@…>, 20 years ago

Begin MIPS implementation of 4-level page table interface.

Add email address to each item in doc/AUTHORS.

Correct type names in comments in mm/vm.c.
Introduce ptl0 pointer in vm_t.

  • Property mode set to 100644
File size: 2.3 KB
RevLine 
[f761f1eb]1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __mips_TLB_H__
30#define __mips_TLB_H__
31
[a1a03f9]32#define PAGE_UNCACHED 2
33#define PAGE_CACHEABLE_EXC_WRITE 5
34
[f761f1eb]35struct entry_lo {
[a1a03f9]36 unsigned g : 1; /* global bit */
37 unsigned v : 1; /* valid bit */
38 unsigned d : 1; /* dirty/write-protect bit */
39 unsigned c : 3; /* cache coherency attribute */
40 unsigned pfn : 24; /* frame number */
[f761f1eb]41 unsigned : 2;
42} __attribute__ ((packed));
43
44struct entry_hi {
45 unsigned asid : 8;
46 unsigned : 4;
47 unsigned g : 1;
48 unsigned vpn2 : 19;
49} __attribute__ ((packed));
50
51struct page_mask {
52 unsigned : 13;
53 unsigned mask : 12;
54 unsigned : 7;
55} __attribute__ ((packed));
56
57struct tlb_entry {
58 struct entry_lo lo0;
59 struct entry_lo lo1;
60 struct entry_hi hi;
61 struct page_mask mask;
62} __attribute__ ((packed));
63
[a1a03f9]64typedef struct entry_lo pte_t;
65
[f761f1eb]66extern void tlb_refill(void);
67extern void tlb_invalid(void);
68
69#endif
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