| [f761f1eb] | 1 | /*
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| [178ec7b] | 2 | * Copyright (C) 2003-2004 Jakub Jermar
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| [f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #ifndef __CP0_H__
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| 30 | #define __CP0_H__
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| 31 |
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| 32 | #include <arch/types.h>
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| 33 |
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| 34 | #define cp0_status_ie_enabled_bit (1<<0)
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| 35 | #define cp0_status_exl_exception_bit (1<<1)
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| 36 | #define cp0_status_erl_error_bit (1<<2)
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| [2bd4fdf] | 37 | #define cp0_status_um_bit (1<<4)
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| [ffc277e] | 38 | #define cp0_status_bev_bootstrap_bit (1<<22)
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| 39 | #define cp0_status_fpu_bit (1<<29)
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| [f761f1eb] | 40 |
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| 41 | #define cp0_status_im7_shift 15
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| 42 | /*
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| 43 | * Magic value for use in msim.
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| 44 | * On AMD Duron 800Mhz, this roughly seems like one us.
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| 45 | */
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| 46 | #define cp0_compare_value 10000
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| 47 |
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| [ffc277e] | 48 | static inline void tlbp(void)
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| 49 | {
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| 50 | __asm__ volatile ("tlbp");
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| 51 | }
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| 52 |
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| 53 | static inline void tlbr(void)
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| 54 | {
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| 55 | __asm__ volatile ("tlbr");
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| 56 | }
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| 57 | static inline void tlbwi(void)
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| 58 | {
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| 59 | __asm__ volatile ("tlbwi");
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| 60 | }
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| 61 | static inline void tlbwr(void)
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| 62 | {
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| 63 | __asm__ volatile ("tlbwr");
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| 64 | }
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| 65 |
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| 66 |
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| 67 |
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| [f761f1eb] | 68 | extern __u32 cp0_index_read(void);
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| 69 | extern void cp0_idnex_write(__u32 val);
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| 70 |
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| 71 | extern __u32 cp0_random_read(void);
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| 72 |
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| 73 | extern __u32 cp0_entry_lo0_read(void);
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| 74 | extern void cp0_entry_lo0_write(__u32 val);
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| 75 |
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| 76 | extern __u32 cp0_entry_lo1_read(void);
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| 77 | extern void cp0_entry_lo1_write(__u32 val);
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| 78 |
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| 79 | extern __u32 cp0_context_read(void);
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| 80 | extern void cp0_context_write(__u32 val);
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| 81 |
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| 82 | extern __u32 cp0_pagemask_read(void);
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| 83 | extern void cp0_pagemask_write(__u32 val);
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| 84 |
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| 85 | extern __u32 cp0_wired_read(void);
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| 86 | extern void cp0_wired_write(__u32 val);
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| 87 |
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| 88 | extern __u32 cp0_badvaddr_read(void);
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| 89 |
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| 90 | extern volatile __u32 cp0_count_read(void);
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| 91 | extern void cp0_count_write(__u32 val);
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| 92 |
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| 93 | extern volatile __u32 cp0_entry_hi_read(void);
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| 94 | extern void cp0_entry_hi_write(__u32 val);
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| 95 |
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| 96 | extern volatile __u32 cp0_compare_read(void);
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| 97 | extern void cp0_compare_write(__u32 val);
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| 98 |
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| 99 | extern __u32 cp0_status_read(void);
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| 100 | extern void cp0_status_write(__u32 val);
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| 101 |
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| 102 | extern __u32 cp0_cause_read(void);
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| 103 | extern void cp0_cause_write(__u32 val);
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| 104 |
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| 105 | extern __u32 cp0_epc_read(void);
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| 106 | extern void cp0_epc_write(__u32 val);
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| 107 |
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| 108 | extern __u32 cp0_prid_read(void);
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| 109 |
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| 110 | #endif
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