source: mainline/arch/ia64/src/mm/tlb.c@ bc78c75

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since bc78c75 was bc78c75, checked in by Jakub Vana <jakub.vana@…>, 19 years ago

IA-64 TLB filling functions for dynamic tlb filling (TC tlb).
  • Property mode set to 100644
File size: 4.1 KB
Line 
1/*
2 * Copyright (C) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/*
30 * TLB management.
31 */
32
33#include <mm/tlb.h>
34#include <arch/mm/tlb.h>
35
36
37/** Invalidate all TLB entries. */
38void tlb_invalidate_all(void)
39{
40 /* TODO */
41}
42
43/** Invalidate entries belonging to an address space.
44 *
45 * @param asid Address space identifier.
46 */
47void tlb_invalidate_asid(asid_t asid)
48{
49 /* TODO */
50}
51
52
53
54void tlb_fill_data(__address va,asid_t asid,vhpt_entry_t entry)
55{
56 region_register rr;
57
58
59 if(!(entry.not_present.p)) return;
60
61 rr.word=rr_read(VA_REGION(va));
62
63 if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
64 {
65 asm
66 (
67 "srlz.i;;\n"
68 "srlz.d;;\n"
69 "mov r8=psr;;\n"
70 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
71 "mov psr.l=r9;;\n"
72 "srlz.d;;\n"
73 "srlz.i;;\n"
74 "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
75 "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
76 "itc.d %3;;\n" /*entry.word[0]*/
77 "mov psr.l=r8;;\n"
78 "srlz.d;;\n"
79 :
80 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
81 :"r8","r9"
82 );
83 }
84 else
85 {
86 region_register rr0;
87 rr0=rr;
88 rr0.map.rid=ASID2RID(asid,VA_REGION(va));
89 rr_write(VA_REGION(va),rr0.word);
90 asm
91 (
92 "mov r8=psr;;\n"
93 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
94 "mov psr.l=r9;;\n"
95 "srlz.d;;\n"
96 "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
97 "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
98 "itc.d %3;;\n" /*entry.word[0]*/
99 "mov psr.l=r8;;\n"
100 "srlz.d;;\n"
101 :
102 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
103 :"r8","r9"
104 );
105 rr_write(VA_REGION(va),rr.word);
106 }
107
108
109}
110
111void tlb_fill_code(__address va,asid_t asid,vhpt_entry_t entry)
112{
113 region_register rr;
114
115
116 if(!(entry.not_present.p)) return;
117
118 rr.word=rr_read(VA_REGION(va));
119
120 if(rr.map.rid==ASID2RID(asid,VA_REGION(va)))
121 {
122 asm
123 (
124 "srlz.i;;\n"
125 "srlz.d;;\n"
126 "mov r8=psr;;\n"
127 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
128 "mov psr.l=r9;;\n"
129 "srlz.d;;\n"
130 "srlz.i;;\n"
131 "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
132 "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
133 "itc.i %3;;\n" /*entry.word[0]*/
134 "mov psr.l=r8;;\n"
135 "srlz.d;;\n"
136 :
137 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
138 :"r8","r9"
139 );
140 }
141 else
142 {
143 region_register rr0;
144 rr0=rr;
145 rr0.map.rid=ASID2RID(asid,VA_REGION(va));
146 rr_write(VA_REGION(va),rr0.word);
147 asm
148 (
149 "mov r8=psr;;\n"
150 "and r9=r8,%0;;\n" /*(~PSR_IC_MASK)*/
151 "mov psr.l=r9;;\n"
152 "srlz.d;;\n"
153 "mov cr20=%1\n" /*va*/ /*cr20 == IFA*/
154 "mov cr21=%2;;\n" /*entry.word[1]*/ /*cr21=ITIR*/
155 "itc.i %3;;\n" /*entry.word[0]*/
156 "mov psr.l=r8;;\n"
157 "srlz.d;;\n"
158 :
159 :"r"(~PSR_IC_MASK),"r"(va),"r"(entry.word[1]),"r"(entry.word[0])
160 :"r8","r9"
161 );
162 rr_write(VA_REGION(va),rr.word);
163 }
164
165
166}
167
168
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