source: mainline/arch/ia64/src/mm/page.c@ 5c3243e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5c3243e was f5935ed, checked in by Jakub Jermar <jakub@…>, 19 years ago

Use hash_table_get_instance instead of list_get_instance.
Rename page_operations to page_mapping_operations.
Rename page_pt_operations to pt_mapping_operations.
Rename page_ht_operations to ht_mapping_operations.

  • Property mode set to 100644
File size: 6.2 KB
Line 
1/*
2 * Copyright (C) 2006 Jakub Jermar
3 * Copyright (C) 2006 Jakub Vana
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include <arch/mm/page.h>
31#include <genarch/mm/page_ht.h>
32#include <mm/asid.h>
33#include <arch/mm/asid.h>
34#include <arch/types.h>
35#include <typedefs.h>
36#include <print.h>
37#include <mm/page.h>
38#include <mm/frame.h>
39#include <config.h>
40#include <panic.h>
41#include <arch/asm.h>
42#include <arch/barrier.h>
43#include <memstr.h>
44
45static void set_environment(void);
46
47/** Initialize ia64 virtual address translation subsystem. */
48void page_arch_init(void)
49{
50 page_mapping_operations = &ht_mapping_operations;
51 pk_disable();
52 set_environment();
53}
54
55/** Initialize VHPT and region registers. */
56void set_environment(void)
57{
58 region_register rr;
59 pta_register pta;
60 int i;
61
62 /*
63 * First set up kernel region register.
64 */
65 rr.word = rr_read(VRN_KERNEL);
66 rr.map.ve = 0; /* disable VHPT walker */
67 rr.map.ps = PAGE_WIDTH;
68 rr.map.rid = ASID_KERNEL;
69 rr_write(VRN_KERNEL, rr.word);
70 srlz_i();
71 srlz_d();
72
73 /*
74 * And invalidate the rest of region register.
75 */
76 for(i = 0; i < REGION_REGISTERS; i++) {
77 /* skip kernel rr */
78 if (i == VRN_KERNEL)
79 continue;
80
81 rr.word == rr_read(i);
82 rr.map.ve = 0; /* disable VHPT walker */
83 rr.map.rid = ASID_INVALID;
84 rr_write(i, rr.word);
85 srlz_i();
86 srlz_d();
87 }
88
89 /*
90 * Set up PTA register.
91 */
92 pta.word = pta_read();
93 pta.map.ve = 0; /* disable VHPT walker */
94 pta.map.vf = 1; /* large entry format */
95 pta.map.size = VHPT_WIDTH;
96 pta.map.base = VHPT_BASE >> PTA_BASE_SHIFT;
97 pta_write(pta.word);
98 srlz_i();
99 srlz_d();
100}
101
102/** Calculate address of collision chain from VPN and ASID.
103 *
104 * Interrupts must be disabled.
105 *
106 * @param page Address of virtual page including VRN bits.
107 * @param asid Address space identifier.
108 *
109 * @return VHPT entry address.
110 */
111vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
112{
113 region_register rr_save, rr;
114 index_t vrn;
115 rid_t rid;
116 vhpt_entry_t *v;
117
118 vrn = page >> VRN_SHIFT;
119 rid = ASID2RID(asid, vrn);
120
121 rr_save.word = rr_read(vrn);
122 if (rr_save.map.rid == rid) {
123 /*
124 * The RID is already in place, compute thash and return.
125 */
126 v = (vhpt_entry_t *) thash(page);
127 return v;
128 }
129
130 /*
131 * The RID must be written to some region register.
132 * To speed things up, register indexed by vrn is used.
133 */
134 rr.word = rr_save.word;
135 rr.map.rid = rid;
136 rr_write(vrn, rr.word);
137 srlz_i();
138 v = (vhpt_entry_t *) thash(page);
139 rr_write(vrn, rr_save.word);
140 srlz_i();
141 srlz_d();
142
143 return v;
144}
145
146/** Compare ASID and VPN against PTE.
147 *
148 * Interrupts must be disabled.
149 *
150 * @param page Address of virtual page including VRN bits.
151 * @param asid Address space identifier.
152 *
153 * @return True if page and asid match the page and asid of t, false otherwise.
154 */
155bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
156{
157 region_register rr_save, rr;
158 index_t vrn;
159 rid_t rid;
160 bool match;
161
162 ASSERT(v);
163
164 vrn = page >> VRN_SHIFT;
165 rid = ASID2RID(asid, vrn);
166
167 rr_save.word = rr_read(vrn);
168 if (rr_save.map.rid == rid) {
169 /*
170 * The RID is already in place, compare ttag with t and return.
171 */
172 return ttag(page) == v->present.tag.tag_word;
173 }
174
175 /*
176 * The RID must be written to some region register.
177 * To speed things up, register indexed by vrn is used.
178 */
179 rr.word = rr_save.word;
180 rr.map.rid = rid;
181 rr_write(vrn, rr.word);
182 srlz_i();
183 match = (ttag(page) == v->present.tag.tag_word);
184 rr_write(vrn, rr_save.word);
185 srlz_i();
186 srlz_d();
187
188 return match;
189}
190
191/** Set up one VHPT entry.
192 *
193 * @param t VHPT entry to be set up.
194 * @param page Virtual address of the page mapped by the entry.
195 * @param asid Address space identifier of the address space to which page belongs.
196 * @param frame Physical address of the frame to wich page is mapped.
197 * @param flags Different flags for the mapping.
198 */
199void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
200{
201 region_register rr_save, rr;
202 index_t vrn;
203 rid_t rid;
204 __u64 tag;
205
206 ASSERT(v);
207
208 vrn = page >> VRN_SHIFT;
209 rid = ASID2RID(asid, vrn);
210
211 /*
212 * Compute ttag.
213 */
214 rr_save.word = rr_read(vrn);
215 rr.word = rr_save.word;
216 rr.map.rid = rid;
217 rr_write(vrn, rr.word);
218 srlz_i();
219 tag = ttag(page);
220 rr_write(vrn, rr_save.word);
221 srlz_i();
222 srlz_d();
223
224 /*
225 * Clear the entry.
226 */
227 v->word[0] = 0;
228 v->word[1] = 0;
229 v->word[2] = 0;
230 v->word[3] = 0;
231
232 v->present.p = true;
233 v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
234 v->present.a = false; /* not accessed */
235 v->present.d = false; /* not dirty */
236 v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
237 v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
238 v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
239 v->present.ppn = frame >> PPN_SHIFT;
240 v->present.ed = false; /* exception not deffered */
241 v->present.ps = PAGE_WIDTH;
242 v->present.key = 0;
243 v->present.tag.tag_word = tag;
244}
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