| 1 | #
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| 2 | # Copyright (C) 2005 Jakub Vana
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| 3 | # Copyright (C) 2005 Jakub Jermar
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| 4 | # All rights reserved.
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| 5 | #
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| 6 | # Redistribution and use in source and binary forms, with or without
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| 7 | # modification, are permitted provided that the following conditions
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| 8 | # are met:
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| 9 | #
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| 10 | # - Redistributions of source code must retain the above copyright
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| 11 | # notice, this list of conditions and the following disclaimer.
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| 12 | # - Redistributions in binary form must reproduce the above copyright
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| 13 | # notice, this list of conditions and the following disclaimer in the
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| 14 | # documentation and/or other materials provided with the distribution.
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| 15 | # - The name of the author may not be used to endorse or promote products
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| 16 | # derived from this software without specific prior written permission.
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| 17 | #
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| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | #
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| 29 |
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| 30 | #include <arch/stack.h>
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| 31 | #include <arch/register.h>
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| 32 |
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| 33 | #define STACK_ITEMS 12
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| 34 | #define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
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| 35 |
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| 36 | #if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
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| 37 | #error Memory stack must be 16-byte aligned.
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| 38 | #endif
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| 39 |
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| 40 | /** Heavyweight interrupt handler
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| 41 | *
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| 42 | * This macro roughly follows steps from 1 to 19 described in
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| 43 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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| 44 | *
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| 45 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
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| 46 | * This goal is achieved by using procedure calls after RSE becomes operational.
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| 47 | *
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| 48 | * Some steps are skipped (enabling and disabling interrupts).
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| 49 | * Some steps are not fully supported yet (e.g. interruptions
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| 50 | * from userspace and floating-point context).
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| 51 | *
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| 52 | * @param offs Offset from the beginning of IVT.
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| 53 | * @param handler Interrupt handler address.
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| 54 | */
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| 55 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
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| 56 | .org ivt + \offs
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| 57 | mov r24 = \offs
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| 58 | movl r25 = \handler ;;
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| 59 | mov ar.k0 = r24
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| 60 | mov ar.k1 = r25
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| 61 | br heavyweight_handler
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| 62 | .endm
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| 63 |
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| 64 | .global heavyweight_handler
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| 65 | heavyweight_handler:
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| 66 | /* 1. copy interrupt registers into bank 0 */
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| 67 | mov r24 = cr.iip
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| 68 | mov r25 = cr.ipsr
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| 69 | mov r26 = cr.iipa
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| 70 | mov r27 = cr.isr
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| 71 | mov r28 = cr.ifa
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| 72 |
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| 73 | /* 2. preserve predicate register into bank 0 */
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| 74 | mov r29 = pr ;;
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| 75 |
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| 76 | /* 3. switch to kernel memory stack */
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| 77 | /* TODO: support interruptions from userspace */
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| 78 | /* assume kernel stack */
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| 79 |
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| 80 | add r31 = -8, r12 ;;
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| 81 | add r12 = -STACK_FRAME_SIZE, r12
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| 82 |
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| 83 | /* 4. save registers in bank 0 into memory stack */
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| 84 | st8 [r31] = r29, -8 ;; /* save predicate registers */
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| 85 |
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| 86 | st8 [r31] = r24, -8 ;; /* save cr.iip */
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| 87 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */
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| 88 | st8 [r31] = r26, -8 ;; /* save cr.iipa */
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| 89 | st8 [r31] = r27, -8 ;; /* save cr.isr */
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| 90 | st8 [r31] = r28, -8 /* save cr.ifa */
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| 91 |
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| 92 | /* 5. RSE switch from interrupted context */
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| 93 | mov r24 = ar.rsc
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| 94 | mov r25 = ar.pfs
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| 95 | cover
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| 96 | mov r26 = cr.ifs
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| 97 |
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| 98 | st8 [r31] = r24, -8;; /* save ar.rsc */
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| 99 | st8 [r31] = r25, -8;; /* save ar.pfs */
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| 100 | st8 [r31] = r26, -8 /* save ar.ifs */
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| 101 |
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| 102 | and r30 = ~3, r24 ;;
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| 103 | mov ar.rsc = r30 ;; /* place RSE in enforced lazy mode */
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| 104 |
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| 105 | mov r27 = ar.rnat
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| 106 | mov r28 = ar.bspstore ;;
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| 107 |
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| 108 | /* assume kernel backing store */
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| 109 | /* mov ar.bspstore = r28 ;; */
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| 110 |
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| 111 | mov r29 = ar.bsp
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| 112 |
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| 113 | st8 [r31] = r27, -8 ;; /* save ar.rnat */
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| 114 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */
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| 115 | st8 [r31] = r29, -8 /* save ar.bsp */
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| 116 |
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| 117 | mov ar.rsc = r24 /* restore RSE's setting */
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| 118 |
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| 119 | /* steps 6 - 15 are done by heavyweight_handler_inner() */
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| 120 | mov r24 = b0 /* save b0 belonging to interrupted context */
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| 121 | mov r26 = ar.k0
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| 122 | mov r25 = ar.k1
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| 123 | br.call.sptk.many rp = heavyweight_handler_inner
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| 124 | 0: mov b0 = r24 /* restore b0 belonging to the interrupted context */
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| 125 |
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| 126 | /* 16. RSE switch to interrupted context */
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| 127 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
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| 128 |
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| 129 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
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| 130 |
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| 131 | mov r28 = ar.bspstore /* calculate loadrs (step 2) */
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| 132 | ld8 r29 = [r31], +8 ;; /* load ar.bsp */
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| 133 | sub r27 = r29 , r28 ;;
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| 134 | shl r27 = r27, 16
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| 135 |
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| 136 | mov r24 = ar.rsc ;;
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| 137 | and r30 = ~3, r24 ;;
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| 138 | or r24 = r30 , r27 ;;
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| 139 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
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| 140 |
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| 141 | loadrs /* (step 3) */
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| 142 |
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| 143 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore */
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| 144 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */
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| 145 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */
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| 146 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */
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| 147 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */
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| 148 |
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| 149 | /* mov ar.bspstore = r28 ;; */ /* (step 4) */
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| 150 | /* mov ar.rnat = r27 */ /* (step 5) */
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| 151 |
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| 152 | mov ar.pfs = r25 /* (step 6) */
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| 153 | mov cr.ifs = r26
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| 154 |
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| 155 | mov ar.rsc = r24 /* (step 7) */
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| 156 |
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| 157 | /* 17. restore interruption state from memory stack */
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| 158 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */
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| 159 | ld8 r27 = [r31], +8 ;; /* load cr.isr */
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| 160 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */
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| 161 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
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| 162 | ld8 r24 = [r31], +8 ;; /* load cr.iip */
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| 163 |
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| 164 | mov cr.iip = r24
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| 165 | mov cr.ipsr = r25
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| 166 | mov cr.iipa = r26
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| 167 | mov cr.isr = r27
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| 168 | mov cr.ifa = r28
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| 169 |
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| 170 | /* 18. restore predicate registers from memory stack */
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| 171 | ld8 r29 = [r31] , -8 ;; /* load predicate registers */
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| 172 | mov pr = r29
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| 173 |
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| 174 | /* 19. return from interruption */
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| 175 | add r12 = STACK_FRAME_SIZE, r12
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| 176 | rfi ;;
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| 177 |
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| 178 | .global heavyweight_handler_inner
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| 179 | heavyweight_handler_inner:
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| 180 | /*
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| 181 | * From this point, the rest of the interrupted context
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| 182 | * will be preserved in stacked registers and backing store.
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| 183 | */
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| 184 | alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
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| 185 |
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| 186 | /* bank 0 is going to be shadowed, copy essential data from there */
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| 187 | mov loc1 = r24 /* b0 belonging to interrupted context */
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| 188 | mov loc2 = r25
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| 189 | mov out0 = r26
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| 190 |
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| 191 | add out1 = STACK_SCRATCH_AREA_SIZE, r12
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| 192 |
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| 193 | /* 6. switch to bank 1 and reenable PSR.ic */
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| 194 | ssm PSR_IC_MASK
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| 195 | bsw.1 ;;
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| 196 | srlz.d
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| 197 |
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| 198 | /* 7. preserve branch and application registers */
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| 199 | mov loc3 = ar.unat
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| 200 | mov loc4 = ar.lc
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| 201 | mov loc5 = ar.ec
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| 202 | mov loc6 = ar.ccv
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| 203 | mov loc7 = ar.csd
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| 204 | mov loc8 = ar.ssd
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| 205 |
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| 206 | mov loc9 = b0
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| 207 | mov loc10 = b1
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| 208 | mov loc11 = b2
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| 209 | mov loc12 = b3
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| 210 | mov loc13 = b4
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| 211 | mov loc14 = b5
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| 212 | mov loc15 = b6
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| 213 | mov loc16 = b7
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| 214 |
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| 215 | /* 8. preserve general and floating-point registers */
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| 216 | /* TODO: save floating-point context */
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| 217 | mov loc17 = r1
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| 218 | mov loc18 = r2
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| 219 | mov loc19 = r3
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| 220 | mov loc20 = r4
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| 221 | mov loc21 = r5
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| 222 | mov loc22 = r6
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| 223 | mov loc23 = r7
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| 224 | mov loc24 = r8
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| 225 | mov loc25 = r9
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| 226 | mov loc26 = r10
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| 227 | mov loc27 = r11
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| 228 | /* skip r12 (stack pointer) */
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| 229 | mov loc28 = r13
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| 230 | mov loc29 = r14
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| 231 | mov loc30 = r15
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| 232 | mov loc31 = r16
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| 233 | mov loc32 = r17
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| 234 | mov loc33 = r18
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| 235 | mov loc34 = r19
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| 236 | mov loc35 = r20
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| 237 | mov loc36 = r21
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| 238 | mov loc37 = r22
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| 239 | mov loc38 = r23
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| 240 | mov loc39 = r24
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| 241 | mov loc40 = r25
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| 242 | mov loc41 = r26
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| 243 | mov loc42 = r27
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| 244 | mov loc43 = r28
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| 245 | mov loc44 = r29
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| 246 | mov loc45 = r30
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| 247 | mov loc46 = r31
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| 248 |
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| 249 | /* 9. skipped (will not enable interrupts) */
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| 250 | /*
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| 251 | * ssm PSR_I_MASK
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| 252 | * ;;
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| 253 | * srlz.d
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| 254 | */
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| 255 |
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| 256 | /* 10. call handler */
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| 257 | mov b1 = loc2
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| 258 | br.call.sptk.many b0 = b1
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| 259 |
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| 260 | /* 11. return from handler */
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| 261 | 0:
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| 262 |
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| 263 | /* 12. skipped (will not disable interrupts) */
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| 264 | /*
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| 265 | * rsm PSR_I_MASK
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| 266 | * ;;
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| 267 | * srlz.d
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| 268 | */
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| 269 |
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| 270 | /* 13. restore general and floating-point registers */
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| 271 | /* TODO: restore floating-point context */
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| 272 | mov r1 = loc17
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| 273 | mov r2 = loc18
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| 274 | mov r3 = loc19
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| 275 | mov r4 = loc20
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| 276 | mov r5 = loc21
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| 277 | mov r6 = loc22
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| 278 | mov r7 = loc23
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| 279 | mov r8 = loc24
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| 280 | mov r9 = loc25
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| 281 | mov r10 = loc26
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| 282 | mov r11 = loc27
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| 283 | /* skip r12 (stack pointer) */
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| 284 | mov r13 = loc28
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| 285 | mov r14 = loc29
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| 286 | mov r15 = loc30
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| 287 | mov r16 = loc31
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| 288 | mov r17 = loc32
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| 289 | mov r18 = loc33
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| 290 | mov r19 = loc34
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| 291 | mov r20 = loc35
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| 292 | mov r21 = loc36
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| 293 | mov r22 = loc37
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| 294 | mov r23 = loc38
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| 295 | mov r24 = loc39
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| 296 | mov r25 = loc40
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| 297 | mov r26 = loc41
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| 298 | mov r27 = loc42
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| 299 | mov r28 = loc43
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| 300 | mov r29 = loc44
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| 301 | mov r30 = loc45
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| 302 | mov r31 = loc46
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| 303 |
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| 304 | /* 14. restore branch and application registers */
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| 305 | mov ar.unat = loc3
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| 306 | mov ar.lc = loc4
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| 307 | mov ar.ec = loc5
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| 308 | mov ar.ccv = loc6
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| 309 | mov ar.csd = loc7
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| 310 | mov ar.ssd = loc8
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| 311 |
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| 312 | mov b0 = loc9
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| 313 | mov b1 = loc10
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| 314 | mov b2 = loc11
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| 315 | mov b3 = loc12
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| 316 | mov b4 = loc13
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| 317 | mov b5 = loc14
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| 318 | mov b6 = loc15
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| 319 | mov b7 = loc16
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| 320 |
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| 321 | /* 15. disable PSR.ic and switch to bank 0 */
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| 322 | rsm PSR_IC_MASK
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| 323 | bsw.0 ;;
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| 324 | srlz.d
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| 325 |
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| 326 | mov r24 = loc1
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| 327 | mov ar.pfs = loc0
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| 328 | br.ret.sptk.many b0
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| 329 |
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| 330 | .global ivt
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| 331 | .align 32768
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| 332 | ivt:
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| 333 | HEAVYWEIGHT_HANDLER 0x0000
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| 334 | HEAVYWEIGHT_HANDLER 0x0400
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| 335 | HEAVYWEIGHT_HANDLER 0x0800
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| 336 | HEAVYWEIGHT_HANDLER 0x0c00
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| 337 | HEAVYWEIGHT_HANDLER 0x1000
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| 338 | HEAVYWEIGHT_HANDLER 0x1400
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| 339 | HEAVYWEIGHT_HANDLER 0x1800
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| 340 | HEAVYWEIGHT_HANDLER 0x1c00
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| 341 | HEAVYWEIGHT_HANDLER 0x2000
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| 342 | HEAVYWEIGHT_HANDLER 0x2400
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| 343 | HEAVYWEIGHT_HANDLER 0x2800
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| 344 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
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| 345 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
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| 346 | HEAVYWEIGHT_HANDLER 0x3400
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| 347 | HEAVYWEIGHT_HANDLER 0x3800
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| 348 | HEAVYWEIGHT_HANDLER 0x3c00
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| 349 | HEAVYWEIGHT_HANDLER 0x4000
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| 350 | HEAVYWEIGHT_HANDLER 0x4400
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| 351 | HEAVYWEIGHT_HANDLER 0x4800
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| 352 | HEAVYWEIGHT_HANDLER 0x4c00
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| 353 |
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| 354 | HEAVYWEIGHT_HANDLER 0x5000
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| 355 | HEAVYWEIGHT_HANDLER 0x5100
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| 356 | HEAVYWEIGHT_HANDLER 0x5200
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| 357 | HEAVYWEIGHT_HANDLER 0x5300
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| 358 | HEAVYWEIGHT_HANDLER 0x5400 general_exception
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| 359 | HEAVYWEIGHT_HANDLER 0x5500
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| 360 | HEAVYWEIGHT_HANDLER 0x5600
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| 361 | HEAVYWEIGHT_HANDLER 0x5700
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| 362 | HEAVYWEIGHT_HANDLER 0x5800
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| 363 | HEAVYWEIGHT_HANDLER 0x5900
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| 364 | HEAVYWEIGHT_HANDLER 0x5a00
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| 365 | HEAVYWEIGHT_HANDLER 0x5b00
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| 366 | HEAVYWEIGHT_HANDLER 0x5c00
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| 367 | HEAVYWEIGHT_HANDLER 0x5d00
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| 368 | HEAVYWEIGHT_HANDLER 0x5e00
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| 369 | HEAVYWEIGHT_HANDLER 0x5f00
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| 370 |
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| 371 | HEAVYWEIGHT_HANDLER 0x6000
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| 372 | HEAVYWEIGHT_HANDLER 0x6100
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| 373 | HEAVYWEIGHT_HANDLER 0x6200
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| 374 | HEAVYWEIGHT_HANDLER 0x6300
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| 375 | HEAVYWEIGHT_HANDLER 0x6400
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| 376 | HEAVYWEIGHT_HANDLER 0x6500
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| 377 | HEAVYWEIGHT_HANDLER 0x6600
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| 378 | HEAVYWEIGHT_HANDLER 0x6700
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| 379 | HEAVYWEIGHT_HANDLER 0x6800
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| 380 | HEAVYWEIGHT_HANDLER 0x6900
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| 381 | HEAVYWEIGHT_HANDLER 0x6a00
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| 382 | HEAVYWEIGHT_HANDLER 0x6b00
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| 383 | HEAVYWEIGHT_HANDLER 0x6c00
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| 384 | HEAVYWEIGHT_HANDLER 0x6d00
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| 385 | HEAVYWEIGHT_HANDLER 0x6e00
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| 386 | HEAVYWEIGHT_HANDLER 0x6f00
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| 387 |
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| 388 | HEAVYWEIGHT_HANDLER 0x7000
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| 389 | HEAVYWEIGHT_HANDLER 0x7100
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| 390 | HEAVYWEIGHT_HANDLER 0x7200
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| 391 | HEAVYWEIGHT_HANDLER 0x7300
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| 392 | HEAVYWEIGHT_HANDLER 0x7400
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| 393 | HEAVYWEIGHT_HANDLER 0x7500
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| 394 | HEAVYWEIGHT_HANDLER 0x7600
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| 395 | HEAVYWEIGHT_HANDLER 0x7700
|
|---|
| 396 | HEAVYWEIGHT_HANDLER 0x7800
|
|---|
| 397 | HEAVYWEIGHT_HANDLER 0x7900
|
|---|
| 398 | HEAVYWEIGHT_HANDLER 0x7a00
|
|---|
| 399 | HEAVYWEIGHT_HANDLER 0x7b00
|
|---|
| 400 | HEAVYWEIGHT_HANDLER 0x7c00
|
|---|
| 401 | HEAVYWEIGHT_HANDLER 0x7d00
|
|---|
| 402 | HEAVYWEIGHT_HANDLER 0x7e00
|
|---|
| 403 | HEAVYWEIGHT_HANDLER 0x7f00
|
|---|
