| 1 | #
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| 2 | # Copyright (C) 2005 Jakub Vana
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| 3 | # Copyright (C) 2005 Jakub Jermar
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| 4 | # All rights reserved.
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| 5 | #
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| 6 | # Redistribution and use in source and binary forms, with or without
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| 7 | # modification, are permitted provided that the following conditions
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| 8 | # are met:
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| 9 | #
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| 10 | # - Redistributions of source code must retain the above copyright
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| 11 | # notice, this list of conditions and the following disclaimer.
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| 12 | # - Redistributions in binary form must reproduce the above copyright
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| 13 | # notice, this list of conditions and the following disclaimer in the
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| 14 | # documentation and/or other materials provided with the distribution.
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| 15 | # - The name of the author may not be used to endorse or promote products
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| 16 | # derived from this software without specific prior written permission.
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| 17 | #
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| 18 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | #
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| 29 |
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| 30 | #include <arch/stack.h>
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| 31 | #include <arch/register.h>
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| 32 | #include <arch/mm/page.h>
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| 33 | #include <align.h>
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| 34 |
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| 35 | #define STACK_ITEMS 13
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| 36 | #define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
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| 37 |
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| 38 | #if (STACK_ITEMS % 2 == 0)
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| 39 | # define STACK_FRAME_BIAS 8
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| 40 | #else
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| 41 | # define STACK_FRAME_BIAS 16
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| 42 | #endif
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| 43 |
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| 44 | /** Partitioning of bank 0 registers. */
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| 45 | #define R_OFFS r16
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| 46 | #define R_HANDLER r17
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| 47 | #define R_RET r18
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| 48 | #define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
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| 49 |
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| 50 | /** Heavyweight interrupt handler
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| 51 | *
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| 52 | * This macro roughly follows steps from 1 to 19 described in
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| 53 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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| 54 | *
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| 55 | * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
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| 56 | * This goal is achieved by using procedure calls after RSE becomes operational.
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| 57 | *
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| 58 | * Some steps are skipped (enabling and disabling interrupts).
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| 59 | * Some steps are not fully supported yet (e.g. interruptions
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| 60 | * from userspace and floating-point context).
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| 61 | *
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| 62 | * @param offs Offset from the beginning of IVT.
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| 63 | * @param handler Interrupt handler address.
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| 64 | */
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| 65 | .macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
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| 66 | .org ivt + \offs
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| 67 | mov R_OFFS = \offs
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| 68 | movl R_HANDLER = \handler ;;
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| 69 | br heavyweight_handler
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| 70 | .endm
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| 71 |
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| 72 | .global heavyweight_handler
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| 73 | heavyweight_handler:
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| 74 | /* 1. copy interrupt registers into bank 0 */
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| 75 |
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| 76 | /*
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| 77 | * Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
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| 78 | */
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| 79 | mov r24 = cr.iip
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| 80 | mov r25 = cr.ipsr
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| 81 | mov r26 = cr.iipa
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| 82 | mov r27 = cr.isr
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| 83 | mov r28 = cr.ifa
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| 84 |
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| 85 | /* 2. preserve predicate register into bank 0 */
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| 86 | mov r29 = pr ;;
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| 87 |
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| 88 | /* 3. switch to kernel memory stack */
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| 89 | mov r30 = cr.ipsr
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| 90 | shr.u r31 = r12, VRN_SHIFT ;;
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| 91 |
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| 92 | /*
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| 93 | * Set p6 to true if the stack register references kernel address space.
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| 94 | * Set p7 to false if the stack register doesn't reference kernel address space.
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| 95 | */
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| 96 | cmp.eq p6, p7 = VRN_KERNEL, r31 ;;
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| 97 |
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| 98 | (p6) shr.u r30 = r30, PSR_CPL_SHIFT ;;
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| 99 | (p6) and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
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| 100 |
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| 101 | /*
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| 102 | * Set p6 to true if the interrupted context executed in kernel mode.
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| 103 | * Set p7 to false if the interrupted context didn't execute in kernel mode.
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| 104 | */
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| 105 | (p6) cmp.eq p6, p7 = r30, r0 ;;
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| 106 |
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| 107 | /*
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| 108 | * Now, p7 is true iff the stack needs to be switched to kernel stack.
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| 109 | */
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| 110 | mov r30 = r12
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| 111 | (p7) mov r12 = R_KSTACK ;;
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| 112 |
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| 113 | add r31 = -STACK_FRAME_BIAS, r12 ;;
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| 114 | add r12 = -STACK_FRAME_SIZE, r12
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| 115 |
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| 116 | /* 4. save registers in bank 0 into memory stack */
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| 117 | st8 [r31] = r30, -8 ;; /* save old stack pointer */
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| 118 |
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| 119 | st8 [r31] = r29, -8 ;; /* save predicate registers */
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| 120 |
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| 121 | st8 [r31] = r24, -8 ;; /* save cr.iip */
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| 122 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */
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| 123 | st8 [r31] = r26, -8 ;; /* save cr.iipa */
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| 124 | st8 [r31] = r27, -8 ;; /* save cr.isr */
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| 125 | st8 [r31] = r28, -8 ;; /* save cr.ifa */
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| 126 |
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| 127 | /* 5. RSE switch from interrupted context */
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| 128 | mov r24 = ar.rsc
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| 129 | mov r25 = ar.pfs
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| 130 | cover
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| 131 | mov r26 = cr.ifs
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| 132 |
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| 133 | st8 [r31] = r24, -8 ;; /* save ar.rsc */
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| 134 | st8 [r31] = r25, -8 ;; /* save ar.pfs */
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| 135 | st8 [r31] = r26, -8 /* save ar.ifs */
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| 136 |
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| 137 | and r30 = ~3, r24 ;;
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| 138 | mov ar.rsc = r30 ;; /* place RSE in enforced lazy mode */
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| 139 |
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| 140 | mov r27 = ar.rnat
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| 141 | mov r28 = ar.bspstore ;;
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| 142 |
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| 143 | /* assume kernel backing store */
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| 144 | /* mov ar.bspstore = r28 ;; */
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| 145 |
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| 146 | mov r29 = ar.bsp
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| 147 |
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| 148 | st8 [r31] = r27, -8 ;; /* save ar.rnat */
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| 149 | st8 [r31] = r28, -8 ;; /* save ar.bspstore */
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| 150 | st8 [r31] = r29, -8 /* save ar.bsp */
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| 151 |
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| 152 | mov ar.rsc = r24 /* restore RSE's setting */
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| 153 |
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| 154 | /* steps 6 - 15 are done by heavyweight_handler_inner() */
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| 155 | mov R_RET = b0 /* save b0 belonging to interrupted context */
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| 156 | br.call.sptk.many b0 = heavyweight_handler_inner
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| 157 | 0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
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| 158 |
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| 159 | /* 16. RSE switch to interrupted context */
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| 160 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
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| 161 |
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| 162 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 ;;
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| 163 |
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| 164 | mov r28 = ar.bspstore /* calculate loadrs (step 2) */
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| 165 | ld8 r29 = [r31], +8 ;; /* load ar.bsp */
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| 166 | sub r27 = r29 , r28 ;;
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| 167 | shl r27 = r27, 16
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| 168 |
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| 169 | mov r24 = ar.rsc ;;
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| 170 | and r30 = ~3, r24 ;;
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| 171 | or r24 = r30 , r27 ;;
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| 172 | mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
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| 173 |
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| 174 | loadrs /* (step 3) */
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| 175 |
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| 176 | ld8 r28 = [r31], +8 ;; /* load ar.bspstore */
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| 177 | ld8 r27 = [r31], +8 ;; /* load ar.rnat */
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| 178 | ld8 r26 = [r31], +8 ;; /* load cr.ifs */
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| 179 | ld8 r25 = [r31], +8 ;; /* load ar.pfs */
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| 180 | ld8 r24 = [r31], +8 ;; /* load ar.rsc */
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| 181 |
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| 182 | /* mov ar.bspstore = r28 ;; */ /* (step 4) */
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| 183 | /* mov ar.rnat = r27 */ /* (step 5) */
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| 184 |
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| 185 | mov ar.pfs = r25 /* (step 6) */
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| 186 | mov cr.ifs = r26
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| 187 |
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| 188 | mov ar.rsc = r24 /* (step 7) */
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| 189 |
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| 190 | /* 17. restore interruption state from memory stack */
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| 191 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */
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| 192 | ld8 r27 = [r31], +8 ;; /* load cr.isr */
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| 193 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */
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| 194 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
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| 195 | ld8 r24 = [r31], +8 ;; /* load cr.iip */
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| 196 |
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| 197 | mov cr.iip = r24
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| 198 | mov cr.ipsr = r25
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| 199 | mov cr.iipa = r26
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| 200 | mov cr.isr = r27
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| 201 | mov cr.ifa = r28
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| 202 |
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| 203 | /* 18. restore predicate registers from memory stack */
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| 204 | ld8 r29 = [r31], +8 ;; /* load predicate registers */
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| 205 | mov pr = r29
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| 206 |
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| 207 | /* 19. return from interruption */
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| 208 | ld8 r12 = [r31] /* load stack pointer */
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| 209 | rfi ;;
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| 210 |
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| 211 | .global heavyweight_handler_inner
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| 212 | heavyweight_handler_inner:
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| 213 | /*
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| 214 | * From this point, the rest of the interrupted context
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| 215 | * will be preserved in stacked registers and backing store.
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| 216 | */
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| 217 | alloc loc0 = ar.pfs, 0, 47, 2, 0 ;;
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| 218 |
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| 219 | /* bank 0 is going to be shadowed, copy essential data from there */
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| 220 | mov loc1 = R_RET /* b0 belonging to interrupted context */
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| 221 | mov loc2 = R_HANDLER
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| 222 | mov out0 = R_OFFS
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| 223 |
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| 224 | add out1 = STACK_SCRATCH_AREA_SIZE, r12
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| 225 |
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| 226 | /* 6. switch to bank 1 and reenable PSR.ic */
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| 227 | ssm PSR_IC_MASK
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| 228 | bsw.1 ;;
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| 229 | srlz.d
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| 230 |
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| 231 | /* 7. preserve branch and application registers */
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| 232 | mov loc3 = ar.unat
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| 233 | mov loc4 = ar.lc
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| 234 | mov loc5 = ar.ec
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| 235 | mov loc6 = ar.ccv
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| 236 | mov loc7 = ar.csd
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| 237 | mov loc8 = ar.ssd
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| 238 |
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| 239 | mov loc9 = b0
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| 240 | mov loc10 = b1
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| 241 | mov loc11 = b2
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| 242 | mov loc12 = b3
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| 243 | mov loc13 = b4
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| 244 | mov loc14 = b5
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| 245 | mov loc15 = b6
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| 246 | mov loc16 = b7
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| 247 |
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| 248 | /* 8. preserve general and floating-point registers */
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| 249 | /* TODO: save floating-point context */
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| 250 | mov loc17 = r1
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| 251 | mov loc18 = r2
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| 252 | mov loc19 = r3
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| 253 | mov loc20 = r4
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| 254 | mov loc21 = r5
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| 255 | mov loc22 = r6
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| 256 | mov loc23 = r7
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| 257 | mov loc24 = r8
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| 258 | mov loc25 = r9
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| 259 | mov loc26 = r10
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| 260 | mov loc27 = r11
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| 261 | /* skip r12 (stack pointer) */
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| 262 | mov loc28 = r13
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| 263 | mov loc29 = r14
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| 264 | mov loc30 = r15
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| 265 | mov loc31 = r16
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| 266 | mov loc32 = r17
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| 267 | mov loc33 = r18
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| 268 | mov loc34 = r19
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| 269 | mov loc35 = r20
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| 270 | mov loc36 = r21
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| 271 | mov loc37 = r22
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| 272 | mov loc38 = r23
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| 273 | mov loc39 = r24
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| 274 | mov loc40 = r25
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| 275 | mov loc41 = r26
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| 276 | mov loc42 = r27
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| 277 | mov loc43 = r28
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| 278 | mov loc44 = r29
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| 279 | mov loc45 = r30
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| 280 | mov loc46 = r31
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| 281 |
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| 282 | /* 9. skipped (will not enable interrupts) */
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| 283 | /*
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| 284 | * ssm PSR_I_MASK
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| 285 | * ;;
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| 286 | * srlz.d
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| 287 | */
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| 288 |
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| 289 | /* 10. call handler */
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| 290 | mov b1 = loc2
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| 291 | br.call.sptk.many b0 = b1
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| 292 |
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| 293 | /* 11. return from handler */
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| 294 | 0:
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| 295 |
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| 296 | /* 12. skipped (will not disable interrupts) */
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| 297 | /*
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| 298 | * rsm PSR_I_MASK
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| 299 | * ;;
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| 300 | * srlz.d
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| 301 | */
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| 302 |
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| 303 | /* 13. restore general and floating-point registers */
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| 304 | /* TODO: restore floating-point context */
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| 305 | mov r1 = loc17
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| 306 | mov r2 = loc18
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| 307 | mov r3 = loc19
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| 308 | mov r4 = loc20
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| 309 | mov r5 = loc21
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| 310 | mov r6 = loc22
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| 311 | mov r7 = loc23
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| 312 | mov r8 = loc24
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| 313 | mov r9 = loc25
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| 314 | mov r10 = loc26
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| 315 | mov r11 = loc27
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| 316 | /* skip r12 (stack pointer) */
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| 317 | mov r13 = loc28
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| 318 | mov r14 = loc29
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| 319 | mov r15 = loc30
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| 320 | mov r16 = loc31
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| 321 | mov r17 = loc32
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| 322 | mov r18 = loc33
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| 323 | mov r19 = loc34
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| 324 | mov r20 = loc35
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| 325 | mov r21 = loc36
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| 326 | mov r22 = loc37
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| 327 | mov r23 = loc38
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| 328 | mov r24 = loc39
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| 329 | mov r25 = loc40
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| 330 | mov r26 = loc41
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| 331 | mov r27 = loc42
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| 332 | mov r28 = loc43
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| 333 | mov r29 = loc44
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| 334 | mov r30 = loc45
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| 335 | mov r31 = loc46
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| 336 |
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| 337 | /* 14. restore branch and application registers */
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| 338 | mov ar.unat = loc3
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| 339 | mov ar.lc = loc4
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| 340 | mov ar.ec = loc5
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| 341 | mov ar.ccv = loc6
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| 342 | mov ar.csd = loc7
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| 343 | mov ar.ssd = loc8
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| 344 |
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| 345 | mov b0 = loc9
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| 346 | mov b1 = loc10
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| 347 | mov b2 = loc11
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| 348 | mov b3 = loc12
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| 349 | mov b4 = loc13
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| 350 | mov b5 = loc14
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| 351 | mov b6 = loc15
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| 352 | mov b7 = loc16
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| 353 |
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| 354 | /* 15. disable PSR.ic and switch to bank 0 */
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| 355 | rsm PSR_IC_MASK
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| 356 | bsw.0 ;;
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| 357 | srlz.d
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| 358 |
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| 359 | mov R_RET = loc1
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| 360 | mov ar.pfs = loc0
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| 361 | br.ret.sptk.many b0
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| 362 |
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| 363 | .global ivt
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| 364 | .align 32768
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| 365 | ivt:
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| 366 | HEAVYWEIGHT_HANDLER 0x0000
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| 367 | HEAVYWEIGHT_HANDLER 0x0400
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| 368 | HEAVYWEIGHT_HANDLER 0x0800
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| 369 | HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
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| 370 | HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
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| 371 | HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
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| 372 | HEAVYWEIGHT_HANDLER 0x1800
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| 373 | HEAVYWEIGHT_HANDLER 0x1c00
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| 374 | HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
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| 375 | HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
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| 376 | HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
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| 377 | HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
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| 378 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
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| 379 | HEAVYWEIGHT_HANDLER 0x3400
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| 380 | HEAVYWEIGHT_HANDLER 0x3800
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| 381 | HEAVYWEIGHT_HANDLER 0x3c00
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| 382 | HEAVYWEIGHT_HANDLER 0x4000
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| 383 | HEAVYWEIGHT_HANDLER 0x4400
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| 384 | HEAVYWEIGHT_HANDLER 0x4800
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| 385 | HEAVYWEIGHT_HANDLER 0x4c00
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| 386 |
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| 387 | HEAVYWEIGHT_HANDLER 0x5000 page_not_present
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| 388 | HEAVYWEIGHT_HANDLER 0x5100
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| 389 | HEAVYWEIGHT_HANDLER 0x5200
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| 390 | HEAVYWEIGHT_HANDLER 0x5300
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| 391 | HEAVYWEIGHT_HANDLER 0x5400 general_exception
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| 392 | HEAVYWEIGHT_HANDLER 0x5500
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| 393 | HEAVYWEIGHT_HANDLER 0x5600
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| 394 | HEAVYWEIGHT_HANDLER 0x5700
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| 395 | HEAVYWEIGHT_HANDLER 0x5800
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| 396 | HEAVYWEIGHT_HANDLER 0x5900
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| 397 | HEAVYWEIGHT_HANDLER 0x5a00
|
|---|
| 398 | HEAVYWEIGHT_HANDLER 0x5b00
|
|---|
| 399 | HEAVYWEIGHT_HANDLER 0x5c00
|
|---|
| 400 | HEAVYWEIGHT_HANDLER 0x5d00
|
|---|
| 401 | HEAVYWEIGHT_HANDLER 0x5e00
|
|---|
| 402 | HEAVYWEIGHT_HANDLER 0x5f00
|
|---|
| 403 |
|
|---|
| 404 | HEAVYWEIGHT_HANDLER 0x6000
|
|---|
| 405 | HEAVYWEIGHT_HANDLER 0x6100
|
|---|
| 406 | HEAVYWEIGHT_HANDLER 0x6200
|
|---|
| 407 | HEAVYWEIGHT_HANDLER 0x6300
|
|---|
| 408 | HEAVYWEIGHT_HANDLER 0x6400
|
|---|
| 409 | HEAVYWEIGHT_HANDLER 0x6500
|
|---|
| 410 | HEAVYWEIGHT_HANDLER 0x6600
|
|---|
| 411 | HEAVYWEIGHT_HANDLER 0x6700
|
|---|
| 412 | HEAVYWEIGHT_HANDLER 0x6800
|
|---|
| 413 | HEAVYWEIGHT_HANDLER 0x6900
|
|---|
| 414 | HEAVYWEIGHT_HANDLER 0x6a00
|
|---|
| 415 | HEAVYWEIGHT_HANDLER 0x6b00
|
|---|
| 416 | HEAVYWEIGHT_HANDLER 0x6c00
|
|---|
| 417 | HEAVYWEIGHT_HANDLER 0x6d00
|
|---|
| 418 | HEAVYWEIGHT_HANDLER 0x6e00
|
|---|
| 419 | HEAVYWEIGHT_HANDLER 0x6f00
|
|---|
| 420 |
|
|---|
| 421 | HEAVYWEIGHT_HANDLER 0x7000
|
|---|
| 422 | HEAVYWEIGHT_HANDLER 0x7100
|
|---|
| 423 | HEAVYWEIGHT_HANDLER 0x7200
|
|---|
| 424 | HEAVYWEIGHT_HANDLER 0x7300
|
|---|
| 425 | HEAVYWEIGHT_HANDLER 0x7400
|
|---|
| 426 | HEAVYWEIGHT_HANDLER 0x7500
|
|---|
| 427 | HEAVYWEIGHT_HANDLER 0x7600
|
|---|
| 428 | HEAVYWEIGHT_HANDLER 0x7700
|
|---|
| 429 | HEAVYWEIGHT_HANDLER 0x7800
|
|---|
| 430 | HEAVYWEIGHT_HANDLER 0x7900
|
|---|
| 431 | HEAVYWEIGHT_HANDLER 0x7a00
|
|---|
| 432 | HEAVYWEIGHT_HANDLER 0x7b00
|
|---|
| 433 | HEAVYWEIGHT_HANDLER 0x7c00
|
|---|
| 434 | HEAVYWEIGHT_HANDLER 0x7d00
|
|---|
| 435 | HEAVYWEIGHT_HANDLER 0x7e00
|
|---|
| 436 | HEAVYWEIGHT_HANDLER 0x7f00
|
|---|
