source: mainline/arch/ia64/src/interrupt.c@ 6bf18fa

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6bf18fa was 953b0f33, checked in by Jakub Jermar <jakub@…>, 19 years ago

Add dummy IRQ_COUNT and irq_ipc_bind_arch() to ia64, ppc32 and sparc64 so that they compile again.

  • Property mode set to 100644
File size: 6.5 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * Copyright (C) 2005 Jakub Vana
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 */
30
31#include <arch/interrupt.h>
32#include <panic.h>
33#include <print.h>
34#include <console/console.h>
35#include <arch/types.h>
36#include <arch/asm.h>
37#include <arch/barrier.h>
38#include <arch/register.h>
39#include <arch/drivers/it.h>
40#include <arch.h>
41#include <symtab.h>
42#include <debug.h>
43#include <syscall/syscall.h>
44#include <print.h>
45#include <proc/scheduler.h>
46#include <ipc/sysipc.h>
47
48
49#define VECTORS_64_BUNDLE 20
50#define VECTORS_16_BUNDLE 48
51#define VECTORS_16_BUNDLE_START 0x5000
52#define VECTOR_MAX 0x7f00
53
54#define BUNDLE_SIZE 16
55
56char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
57 "VHPT Translation vector",
58 "Instruction TLB vector",
59 "Data TLB vector",
60 "Alternate Instruction TLB vector",
61 "Alternate Data TLB vector",
62 "Data Nested TLB vector",
63 "Instruction Key Miss vector",
64 "Data Key Miss vector",
65 "Dirty-Bit vector",
66 "Instruction Access-Bit vector",
67 "Data Access-Bit vector"
68 "Break Instruction vector",
69 "External Interrupt vector"
70 "Reserved",
71 "Reserved",
72 "Reserved",
73 "Reserved",
74 "Reserved",
75 "Reserved",
76 "Reserved"
77};
78
79char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
80 "Page Not Present vector",
81 "Key Permission vector",
82 "Instruction Access rights vector",
83 "Data Access Rights vector",
84 "General Exception vector",
85 "Disabled FP-Register vector",
86 "NaT Consumption vector",
87 "Speculation vector",
88 "Reserved",
89 "Debug vector",
90 "Unaligned Reference vector",
91 "Unsupported Data Reference vector",
92 "Floating-point Fault vector",
93 "Floating-point Trap vector",
94 "Lower-Privilege Transfer Trap vector",
95 "Taken Branch Trap vector",
96 "Single STep Trap vector",
97 "Reserved",
98 "Reserved",
99 "Reserved",
100 "Reserved",
101 "Reserved",
102 "Reserved",
103 "Reserved",
104 "Reserved",
105 "IA-32 Exception vector",
106 "IA-32 Intercept vector",
107 "IA-32 Interrupt vector",
108 "Reserved",
109 "Reserved",
110 "Reserved"
111};
112
113static char *vector_to_string(__u16 vector);
114static void dump_interrupted_context(istate_t *istate);
115
116char *vector_to_string(__u16 vector)
117{
118 ASSERT(vector <= VECTOR_MAX);
119
120 if (vector >= VECTORS_16_BUNDLE_START)
121 return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)];
122 else
123 return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)];
124}
125
126void dump_interrupted_context(istate_t *istate)
127{
128 char *ifa, *iipa, *iip;
129
130 ifa = get_symtab_entry(istate->cr_ifa);
131 iipa = get_symtab_entry(istate->cr_iipa);
132 iip = get_symtab_entry(istate->cr_iip);
133
134 putchar('\n');
135 printf("Interrupted context dump:\n");
136 printf("ar.bsp=%p\tar.bspstore=%p\n", istate->ar_bsp, istate->ar_bspstore);
137 printf("ar.rnat=%#llx\tar.rsc=%$llx\n", istate->ar_rnat, istate->ar_rsc);
138 printf("ar.ifs=%#llx\tar.pfs=%#llx\n", istate->ar_ifs, istate->ar_pfs);
139 printf("cr.isr=%#llx\tcr.ipsr=%#llx\t\n", istate->cr_isr.value, istate->cr_ipsr);
140
141 printf("cr.iip=%#llx, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei, iip ? iip : "?");
142 printf("cr.iipa=%#llx\t(%s)\n", istate->cr_iipa, iipa ? iipa : "?");
143 printf("cr.ifa=%#llx\t(%s)\n", istate->cr_ifa, ifa ? ifa : "?");
144}
145
146void general_exception(__u64 vector, istate_t *istate)
147{
148 char *desc = "";
149
150 dump_interrupted_context(istate);
151
152 switch (istate->cr_isr.ge_code) {
153 case GE_ILLEGALOP:
154 desc = "Illegal Operation fault";
155 break;
156 case GE_PRIVOP:
157 desc = "Privileged Operation fault";
158 break;
159 case GE_PRIVREG:
160 desc = "Privileged Register fault";
161 break;
162 case GE_RESREGFLD:
163 desc = "Reserved Register/Field fault";
164 break;
165 case GE_DISBLDISTRAN:
166 desc = "Disabled Instruction Set Transition fault";
167 break;
168 case GE_ILLEGALDEP:
169 desc = "Illegal Dependency fault";
170 break;
171 default:
172 desc = "unknown";
173 break;
174 }
175
176 panic("General Exception (%s)\n", desc);
177}
178
179void fpu_enable(void);
180
181void disabled_fp_register(__u64 vector, istate_t *istate)
182{
183#ifdef CONFIG_FPU_LAZY
184 scheduler_fpu_lazy_request();
185#else
186 dump_interrupted_context(istate);
187 panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector));
188#endif
189}
190
191
192void nop_handler(__u64 vector, istate_t *istate)
193{
194}
195
196
197
198/** Handle syscall. */
199int break_instruction(__u64 vector, istate_t *istate)
200{
201 /*
202 * Move to next instruction after BREAK.
203 */
204 if (istate->cr_ipsr.ri == 2) {
205 istate->cr_ipsr.ri = 0;
206 istate->cr_iip += 16;
207 } else {
208 istate->cr_ipsr.ri++;
209 }
210
211 if (istate->in4 < SYSCALL_END)
212 return syscall_table[istate->in4](istate->in0, istate->in1, istate->in2, istate->in3);
213 else
214 panic("Undefined syscall %d", istate->in4);
215
216 return -1;
217}
218
219void universal_handler(__u64 vector, istate_t *istate)
220{
221 dump_interrupted_context(istate);
222 panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector));
223}
224
225void external_interrupt(__u64 vector, istate_t *istate)
226{
227 cr_ivr_t ivr;
228
229 ivr.value = ivr_read();
230 srlz_d();
231
232 switch(ivr.vector) {
233 case INTERRUPT_TIMER:
234 it_interrupt();
235 break;
236 case INTERRUPT_SPURIOUS:
237 printf("cpu%d: spurious interrupt\n", CPU->id);
238 break;
239 default:
240 panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector);
241 break;
242 }
243}
244
245/* Reregister irq to be IPC-ready */
246void irq_ipc_bind_arch(__native irq)
247{
248 panic("not implemented\n");
249 /* TODO */
250}
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