source: mainline/arch/ia64/src/interrupt.c@ 41fa6f2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 41fa6f2 was 41fa6f2, checked in by Jakub Vana <jakub.vana@…>, 19 years ago

Itanium FPU Lazy context switching… but not so much tested

  • Property mode set to 100644
File size: 6.3 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * Copyright (C) 2005 Jakub Vana
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 */
30
31#include <arch/interrupt.h>
32#include <panic.h>
33#include <print.h>
34#include <console/console.h>
35#include <arch/types.h>
36#include <arch/asm.h>
37#include <arch/barrier.h>
38#include <arch/register.h>
39#include <arch/drivers/it.h>
40#include <arch.h>
41#include <symtab.h>
42#include <debug.h>
43#include <syscall/syscall.h>
44#include <print.h>
45#include <proc/scheduler.h>
46
47#define VECTORS_64_BUNDLE 20
48#define VECTORS_16_BUNDLE 48
49#define VECTORS_16_BUNDLE_START 0x5000
50#define VECTOR_MAX 0x7f00
51
52#define BUNDLE_SIZE 16
53
54char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
55 "VHPT Translation vector",
56 "Instruction TLB vector",
57 "Data TLB vector",
58 "Alternate Instruction TLB vector",
59 "Alternate Data TLB vector",
60 "Data Nested TLB vector",
61 "Instruction Key Miss vector",
62 "Data Key Miss vector",
63 "Dirty-Bit vector",
64 "Instruction Access-Bit vector",
65 "Data Access-Bit vector"
66 "Break Instruction vector",
67 "External Interrupt vector"
68 "Reserved",
69 "Reserved",
70 "Reserved",
71 "Reserved",
72 "Reserved",
73 "Reserved",
74 "Reserved"
75};
76
77char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
78 "Page Not Present vector",
79 "Key Permission vector",
80 "Instruction Access rights vector",
81 "Data Access Rights vector",
82 "General Exception vector",
83 "Disabled FP-Register vector",
84 "NaT Consumption vector",
85 "Speculation vector",
86 "Reserved",
87 "Debug vector",
88 "Unaligned Reference vector",
89 "Unsupported Data Reference vector",
90 "Floating-point Fault vector",
91 "Floating-point Trap vector",
92 "Lower-Privilege Transfer Trap vector",
93 "Taken Branch Trap vector",
94 "Single STep Trap vector",
95 "Reserved",
96 "Reserved",
97 "Reserved",
98 "Reserved",
99 "Reserved",
100 "Reserved",
101 "Reserved",
102 "Reserved",
103 "IA-32 Exception vector",
104 "IA-32 Intercept vector",
105 "IA-32 Interrupt vector",
106 "Reserved",
107 "Reserved",
108 "Reserved"
109};
110
111static char *vector_to_string(__u16 vector);
112static void dump_interrupted_context(istate_t *istate);
113
114char *vector_to_string(__u16 vector)
115{
116 ASSERT(vector <= VECTOR_MAX);
117
118 if (vector >= VECTORS_16_BUNDLE_START)
119 return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)];
120 else
121 return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)];
122}
123
124void dump_interrupted_context(istate_t *istate)
125{
126 char *ifa, *iipa, *iip;
127
128 ifa = get_symtab_entry(istate->cr_ifa);
129 iipa = get_symtab_entry(istate->cr_iipa);
130 iip = get_symtab_entry(istate->cr_iip);
131
132 putchar('\n');
133 printf("Interrupted context dump:\n");
134 printf("ar.bsp=%P\tar.bspstore=%P\n", istate->ar_bsp, istate->ar_bspstore);
135 printf("ar.rnat=%Q\tar.rsc=%Q\n", istate->ar_rnat, istate->ar_rsc);
136 printf("ar.ifs=%Q\tar.pfs=%Q\n", istate->ar_ifs, istate->ar_pfs);
137 printf("cr.isr=%Q\tcr.ipsr=%Q\t\n", istate->cr_isr.value, istate->cr_ipsr);
138
139 printf("cr.iip=%Q, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei ,iip ? iip : "?");
140 printf("cr.iipa=%Q\t(%s)\n", istate->cr_iipa, iipa ? iipa : "?");
141 printf("cr.ifa=%Q\t(%s)\n", istate->cr_ifa, ifa ? ifa : "?");
142}
143
144void general_exception(__u64 vector, istate_t *istate)
145{
146 char *desc = "";
147
148 dump_interrupted_context(istate);
149
150 switch (istate->cr_isr.ge_code) {
151 case GE_ILLEGALOP:
152 desc = "Illegal Operation fault";
153 break;
154 case GE_PRIVOP:
155 desc = "Privileged Operation fault";
156 break;
157 case GE_PRIVREG:
158 desc = "Privileged Register fault";
159 break;
160 case GE_RESREGFLD:
161 desc = "Reserved Register/Field fault";
162 break;
163 case GE_DISBLDISTRAN:
164 desc = "Disabled Instruction Set Transition fault";
165 break;
166 case GE_ILLEGALDEP:
167 desc = "Illegal Dependency fault";
168 break;
169 default:
170 desc = "unknown";
171 break;
172 }
173
174 panic("General Exception (%s)\n", desc);
175}
176
177void fpu_enable(void);
178
179void disabled_fp_register(__u64 vector, istate_t *istate)
180{
181#ifdef CONFIG_FPU_LAZY
182 scheduler_fpu_lazy_request();
183#else
184 dump_interrupted_context(istate);
185 panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector));
186#endif
187}
188
189
190void nop_handler(__u64 vector, istate_t *istate)
191{
192}
193
194
195
196/** Handle syscall. */
197int break_instruction(__u64 vector, istate_t *istate)
198{
199 /*
200 * Move to next instruction after BREAK.
201 */
202 if (istate->cr_ipsr.ri == 2) {
203 istate->cr_ipsr.ri = 0;
204 istate->cr_iip += 16;
205 } else {
206 istate->cr_ipsr.ri++;
207 }
208
209 if (istate->in4 < SYSCALL_END)
210 return syscall_table[istate->in4](istate->in0, istate->in1, istate->in2, istate->in3);
211 else
212 panic("Undefined syscall %d", istate->in4);
213
214 return -1;
215}
216
217void universal_handler(__u64 vector, istate_t *istate)
218{
219 dump_interrupted_context(istate);
220 panic("Interruption: %W (%s)\n", (__u16) vector, vector_to_string(vector));
221}
222
223void external_interrupt(__u64 vector, istate_t *istate)
224{
225 cr_ivr_t ivr;
226
227 ivr.value = ivr_read();
228 srlz_d();
229
230 switch(ivr.vector) {
231 case INTERRUPT_TIMER:
232 it_interrupt();
233 break;
234 case INTERRUPT_SPURIOUS:
235 printf("cpu%d: spurious interrupt\n", CPU->id);
236 break;
237 default:
238 panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector);
239 break;
240 }
241}
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