source: mainline/arch/ia64/src/ia64.c@ 39cea6a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 39cea6a was 8e5e78f, checked in by Jakub Vana <jakub.vana@…>, 19 years ago

Thread RSE support completion (kernel)

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch.h>
30#include <arch/ski/ski.h>
31#include <arch/drivers/it.h>
32#include <arch/interrupt.h>
33#include <arch/barrier.h>
34#include <arch/asm.h>
35#include <arch/register.h>
36#include <arch/types.h>
37#include <arch/context.h>
38#include <arch/stack.h>
39#include <arch/mm/page.h>
40#include <mm/as.h>
41#include <config.h>
42#include <userspace.h>
43#include <console/console.h>
44#include <proc/uarg.h>
45#include <syscall/syscall.h>
46
47void arch_pre_mm_init(void)
48{
49 /* Set Interruption Vector Address (i.e. location of interruption vector table). */
50 iva_write((__address) &ivt);
51 srlz_d();
52
53 ski_init_console();
54 it_init();
55
56 /* Setup usermode */
57 init.cnt = 2;
58 init.tasks[0].addr = INIT0_ADDRESS;
59 init.tasks[0].size = INIT0_SIZE;
60 init.tasks[1].addr = INIT1_ADDRESS;
61 init.tasks[1].size = INIT1_SIZE;
62}
63
64void arch_post_mm_init(void)
65{
66}
67
68void arch_pre_smp_init(void)
69{
70}
71
72void arch_post_smp_init(void)
73{
74}
75
76/** Enter userspace and never return. */
77void userspace(uspace_arg_t *kernel_uarg)
78{
79 psr_t psr;
80 rsc_t rsc;
81
82 psr.value = psr_read();
83 psr.cpl = PL_USER;
84 psr.i = true; /* start with interrupts enabled */
85 psr.ic = true;
86 psr.ri = 0; /* start with instruction #0 */
87 psr.bn = 1; /* start in bank 0 */
88
89 __asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
90 rsc.loadrs = 0;
91 rsc.be = false;
92 rsc.pl = PL_USER;
93 rsc.mode = 3; /* eager mode */
94
95 switch_to_userspace((__address) kernel_uarg->uspace_entry,
96 ((__address) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
97 ((__address) kernel_uarg->uspace_stack)+PAGE_SIZE,
98 (__address) kernel_uarg->uspace_uarg,
99 psr.value, rsc.value);
100
101 while (1) {
102 ;
103 }
104}
105
106/** Set thread-local-storage pointer.
107 *
108 * We use r13 (a.k.a. tp) for this purpose.
109 */
110__native sys_tls_set(__native addr)
111{
112 return 0;
113}
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