| 1 | #
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| 2 | # Copyright (C) 2005 Jakub Jermar
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | .text
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| 30 |
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| 31 | .global context_save_arch
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| 32 | .global context_restore_arch
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| 33 |
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| 34 | context_save_arch:
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| 35 | alloc loc0 = ar.pfs, 1, 8, 0, 0
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| 36 | mov loc1 = ar.unat ;;
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| 37 | /* loc2 */
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| 38 | mov loc3 = ar.rsc
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| 39 |
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| 40 | .auto
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| 41 |
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| 42 | /*
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| 43 | * Flush dirty registers to backing store.
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| 44 | * After this ar.bsp and ar.bspstore are equal.
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| 45 | */
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| 46 | flushrs
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| 47 | mov loc4 = ar.bsp
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| 48 |
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| 49 | /*
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| 50 | * Put RSE to enforced lazy mode.
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| 51 | * So that ar.rnat can be read.
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| 52 | */
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| 53 | movl loc5 = ~3
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| 54 | and loc5 = loc3, loc5
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| 55 | mov ar.rsc = loc5
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| 56 | mov loc5 = ar.rnat
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| 57 |
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| 58 | .explicit
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| 59 |
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| 60 | mov loc6 = ar.lc
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| 61 |
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| 62 | /*
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| 63 | * Save application registers
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| 64 | */
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| 65 | st8 [in0] = loc0, 8 ;; /* save ar.pfs */
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| 66 | st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */
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| 67 | mov loc2 = in0 ;;
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| 68 | add in0 = 8, in0 ;; /* skip ar.unat (callee) */
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| 69 | st8 [in0] = loc3, 8 ;; /* save ar.rsc */
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| 70 | st8 [in0] = loc4, 8 ;; /* save ar.bsp */
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| 71 | st8 [in0] = loc5, 8 ;; /* save ar.rnat */
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| 72 | st8 [in0] = loc6, 8 ;; /* save ar.lc */
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| 73 |
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| 74 | /*
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| 75 | * Save general registers including NaT bits
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| 76 | */
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| 77 | st8.spill [in0] = r1, 8 ;;
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| 78 | st8.spill [in0] = r4, 8 ;;
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| 79 | st8.spill [in0] = r5, 8 ;;
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| 80 | st8.spill [in0] = r6, 8 ;;
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| 81 | st8.spill [in0] = r7, 8 ;;
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| 82 | st8.spill [in0] = r12, 8 ;; /* save sp */
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| 83 | st8.spill [in0] = r13, 8 ;;
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| 84 |
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| 85 | mov loc3 = ar.unat ;;
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| 86 | st8 [loc2] = loc3 /* save ar.unat (callee) */
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| 87 |
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| 88 | /*
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| 89 | * Save branch registers
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| 90 | */
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| 91 | mov loc2 = b0 ;;
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| 92 | st8 [in0] = loc2, 8 /* save pc */
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| 93 | mov loc3 = b1 ;;
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| 94 | st8 [in0] = loc3, 8
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| 95 | mov loc4 = b2 ;;
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| 96 | st8 [in0] = loc4, 8
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| 97 | mov loc5 = b3 ;;
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| 98 | st8 [in0] = loc5, 8
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| 99 | mov loc6 = b4 ;;
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| 100 | st8 [in0] = loc6, 8
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| 101 | mov loc7 = b5 ;;
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| 102 | st8 [in0] = loc7, 8
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| 103 |
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| 104 | /*
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| 105 | * Save predicate registers
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| 106 | */
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| 107 | mov loc2 = pr ;;
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| 108 | st8 [in0] = loc2, 8
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| 109 |
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| 110 | mov ar.unat = loc1
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| 111 |
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| 112 | add r8 = r0, r0, 1 /* context_save returns 1 */
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| 113 | br.ret.sptk.many b0
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| 114 |
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| 115 | context_restore_arch:
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| 116 | alloc loc0 = ar.pfs, 1, 9, 0, 0 ;;
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| 117 |
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| 118 | ld8 loc0 = [in0], 8 ;; /* load ar.pfs */
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| 119 | ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */
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| 120 | ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */
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| 121 | ld8 loc3 = [in0], 8 ;; /* load ar.rsc */
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| 122 | ld8 loc4 = [in0], 8 ;; /* load ar.bsp */
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| 123 | ld8 loc5 = [in0], 8 ;; /* load ar.rnat */
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| 124 | ld8 loc6 = [in0], 8 ;; /* load ar.lc */
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| 125 |
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| 126 | .auto
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| 127 |
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| 128 | /*
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| 129 | * Invalidate the ALAT
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| 130 | */
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| 131 | invala
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| 132 |
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| 133 | /*
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| 134 | * Put RSE to enforced lazy mode.
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| 135 | * So that ar.bspstore and ar.rnat can be written.
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| 136 | */
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| 137 | movl loc8 = ~3
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| 138 | and loc8 = loc3, loc8
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| 139 | mov ar.rsc = loc8
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| 140 |
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| 141 | /*
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| 142 | * Flush dirty registers to backing store.
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| 143 | * We do this because we want the following move
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| 144 | * to ar.bspstore to assign the same value to ar.bsp.
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| 145 | */
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| 146 | flushrs
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| 147 |
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| 148 | /*
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| 149 | * Restore application registers
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| 150 | */
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| 151 | mov ar.bspstore = loc4 /* rse.bspload = ar.bsp = ar.bspstore = loc4 */
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| 152 | mov ar.rnat = loc5
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| 153 | mov ar.pfs = loc0
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| 154 | mov ar.rsc = loc3
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| 155 |
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| 156 | .explicit
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| 157 |
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| 158 | mov ar.unat = loc2 ;;
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| 159 | mov ar.lc = loc6
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| 160 |
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| 161 | /*
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| 162 | * Restore general registers including NaT bits
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| 163 | */
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| 164 | ld8.fill r1 = [in0], 8 ;;
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| 165 | ld8.fill r4 = [in0], 8 ;;
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| 166 | ld8.fill r5 = [in0], 8 ;;
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| 167 | ld8.fill r6 = [in0], 8 ;;
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| 168 | ld8.fill r7 = [in0], 8 ;;
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| 169 | ld8.fill r12 = [in0], 8 ;; /* restore sp */
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| 170 | ld8.fill r13 = [in0], 8 ;;
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| 171 |
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| 172 | /*
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| 173 | * Restore branch registers
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| 174 | */
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| 175 | ld8 loc2 = [in0], 8 ;; /* restore pc */
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| 176 | mov b0 = loc2
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| 177 | ld8 loc3 = [in0], 8 ;;
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| 178 | mov b1 = loc3
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| 179 | ld8 loc4 = [in0], 8 ;;
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| 180 | mov b2 = loc4
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| 181 | ld8 loc5 = [in0], 8 ;;
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| 182 | mov b3 = loc5
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| 183 | ld8 loc6 = [in0], 8 ;;
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| 184 | mov b4 = loc6
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| 185 | ld8 loc7 = [in0], 8 ;;
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| 186 | mov b5 = loc7
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| 187 |
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| 188 | /*
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| 189 | * Restore predicate registers
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| 190 | */
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| 191 | ld8 loc2 = [in0], 8 ;;
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| 192 | mov pr = loc2, ~0
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| 193 |
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| 194 | mov ar.unat = loc1
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| 195 |
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| 196 | mov r8 = r0 /* context_restore returns 0 */
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| 197 | br.ret.sptk.many b0
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