source: mainline/arch/ia64/src/context.S@ 9cbd27b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 9cbd27b was 41fa6f2, checked in by Jakub Vana <jakub.vana@…>, 19 years ago

Itanium FPU Lazy context switching… but not so much tested
  • Property mode set to 100644
File size: 5.8 KB
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1#
2# Copyright (C) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10# notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12# notice, this list of conditions and the following disclaimer in the
13# documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15# derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29.text
30
31.global context_save_arch
32.global context_restore_arch
33
34context_save_arch:
35 alloc loc0 = ar.pfs, 1, 8, 0, 0
36 mov loc1 = ar.unat ;;
37 /* loc2 */
38 mov loc3 = ar.rsc
39
40 .auto
41
42 /*
43 * Flush dirty registers to backing store.
44 * After this ar.bsp and ar.bspstore are equal.
45 */
46 flushrs
47 mov loc4 = ar.bsp
48
49 /*
50 * Put RSE to enforced lazy mode.
51 * So that ar.rnat can be read.
52 */
53 and loc5 = ~3, loc3
54 mov ar.rsc = loc5
55 mov loc5 = ar.rnat
56
57 .explicit
58
59 mov loc6 = ar.lc
60
61 /*
62 * Save application registers
63 */
64 st8 [in0] = loc0, 8 ;; /* save ar.pfs */
65 st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */
66 mov loc2 = in0 ;;
67 add in0 = 8, in0 ;; /* skip ar.unat (callee) */
68 st8 [in0] = loc3, 8 ;; /* save ar.rsc */
69 st8 [in0] = loc4, 8 ;; /* save ar.bsp */
70 st8 [in0] = loc5, 8 ;; /* save ar.rnat */
71 st8 [in0] = loc6, 8 ;; /* save ar.lc */
72
73 /*
74 * Save general registers including NaT bits
75 */
76 st8.spill [in0] = r1, 8 ;;
77 st8.spill [in0] = r4, 8 ;;
78 st8.spill [in0] = r5, 8 ;;
79 st8.spill [in0] = r6, 8 ;;
80 st8.spill [in0] = r7, 8 ;;
81 st8.spill [in0] = r12, 8 ;; /* save sp */
82 st8.spill [in0] = r13, 8 ;;
83
84 mov loc3 = ar.unat ;;
85 st8 [loc2] = loc3 /* save ar.unat (callee) */
86
87 /*
88 * Save branch registers
89 */
90 mov loc2 = b0 ;;
91 st8 [in0] = loc2, 8 /* save pc */
92 mov loc3 = b1 ;;
93 st8 [in0] = loc3, 8
94 mov loc4 = b2 ;;
95 st8 [in0] = loc4, 8
96 mov loc5 = b3 ;;
97 st8 [in0] = loc5, 8
98 mov loc6 = b4 ;;
99 st8 [in0] = loc6, 8
100 mov loc7 = b5 ;;
101 st8 [in0] = loc7, 8
102
103 /*
104 * Save predicate registers
105 */
106 mov loc2 = pr ;;
107 st8 [in0] = loc2, 16;; /*Next fpu registers should be spilled to 16B aligned address*/
108
109
110 stf.spill [in0]=f2,16;;
111 stf.spill [in0]=f3,16;;
112 stf.spill [in0]=f4,16;;
113 stf.spill [in0]=f5,16;;
114
115 stf.spill [in0]=f16,16;;
116 stf.spill [in0]=f17,16;;
117 stf.spill [in0]=f18,16;;
118 stf.spill [in0]=f19,16;;
119 stf.spill [in0]=f20,16;;
120 stf.spill [in0]=f21,16;;
121 stf.spill [in0]=f22,16;;
122 stf.spill [in0]=f23,16;;
123 stf.spill [in0]=f24,16;;
124 stf.spill [in0]=f25,16;;
125 stf.spill [in0]=f26,16;;
126 stf.spill [in0]=f27,16;;
127 stf.spill [in0]=f28,16;;
128 stf.spill [in0]=f29,16;;
129 stf.spill [in0]=f30,16;;
130 stf.spill [in0]=f31,16;;
131
132
133 mov ar.unat = loc1
134
135 add r8 = r0, r0, 1 /* context_save returns 1 */
136 br.ret.sptk.many b0
137
138context_restore_arch:
139 alloc loc0 = ar.pfs, 1, 9, 0, 0 ;;
140
141 ld8 loc0 = [in0], 8 ;; /* load ar.pfs */
142 ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */
143 ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */
144 ld8 loc3 = [in0], 8 ;; /* load ar.rsc */
145 ld8 loc4 = [in0], 8 ;; /* load ar.bsp */
146 ld8 loc5 = [in0], 8 ;; /* load ar.rnat */
147 ld8 loc6 = [in0], 8 ;; /* load ar.lc */
148
149 .auto
150
151 /*
152 * Invalidate the ALAT
153 */
154 invala
155
156 /*
157 * Put RSE to enforced lazy mode.
158 * So that ar.bspstore and ar.rnat can be written.
159 */
160 movl loc8 = ~3
161 and loc8 = loc3, loc8
162 mov ar.rsc = loc8
163
164 /*
165 * Flush dirty registers to backing store.
166 * We do this because we want the following move
167 * to ar.bspstore to assign the same value to ar.bsp.
168 */
169 flushrs
170
171 /*
172 * Restore application registers
173 */
174 mov ar.bspstore = loc4 /* rse.bspload = ar.bsp = ar.bspstore = loc4 */
175 mov ar.rnat = loc5
176 mov ar.pfs = loc0
177 mov ar.rsc = loc3
178
179 .explicit
180
181 mov ar.unat = loc2 ;;
182 mov ar.lc = loc6
183
184 /*
185 * Restore general registers including NaT bits
186 */
187 ld8.fill r1 = [in0], 8 ;;
188 ld8.fill r4 = [in0], 8 ;;
189 ld8.fill r5 = [in0], 8 ;;
190 ld8.fill r6 = [in0], 8 ;;
191 ld8.fill r7 = [in0], 8 ;;
192 ld8.fill r12 = [in0], 8 ;; /* restore sp */
193 ld8.fill r13 = [in0], 8 ;;
194
195 /*
196 * Restore branch registers
197 */
198 ld8 loc2 = [in0], 8 ;; /* restore pc */
199 mov b0 = loc2
200 ld8 loc3 = [in0], 8 ;;
201 mov b1 = loc3
202 ld8 loc4 = [in0], 8 ;;
203 mov b2 = loc4
204 ld8 loc5 = [in0], 8 ;;
205 mov b3 = loc5
206 ld8 loc6 = [in0], 8 ;;
207 mov b4 = loc6
208 ld8 loc7 = [in0], 8 ;;
209 mov b5 = loc7
210
211 /*
212 * Restore predicate registers
213 */
214 ld8 loc2 = [in0], 16 ;;
215 mov pr = loc2, ~0
216
217 ldf.fill f2=[in0],16;;
218 ldf.fill f3=[in0],16;;
219 ldf.fill f4=[in0],16;;
220 ldf.fill f5=[in0],16;;
221
222 ldf.fill f16=[in0],16;;
223 ldf.fill f17=[in0],16;;
224 ldf.fill f18=[in0],16;;
225 ldf.fill f19=[in0],16;;
226 ldf.fill f20=[in0],16;;
227 ldf.fill f21=[in0],16;;
228 ldf.fill f22=[in0],16;;
229 ldf.fill f23=[in0],16;;
230 ldf.fill f24=[in0],16;;
231 ldf.fill f25=[in0],16;;
232 ldf.fill f26=[in0],16;;
233 ldf.fill f27=[in0],16;;
234 ldf.fill f28=[in0],16;;
235 ldf.fill f29=[in0],16;;
236 ldf.fill f30=[in0],16;;
237 ldf.fill f31=[in0],16;;
238
239
240
241 mov ar.unat = loc1
242
243 mov r8 = r0 /* context_restore returns 0 */
244 br.ret.sptk.many b0
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