source: mainline/arch/ia64/include/register.h@ 040542aa

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 040542aa was 9e1c942, checked in by Jakub Vana <jakub.vana@…>, 20 years ago

Itanium FPU active context switch
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File size: 7.2 KB
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1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ia64_REGISTER_H__
30#define __ia64_REGISTER_H__
31
32#define CR_IVR_MASK 0xf
33#define PSR_IC_MASK 0x2000
34#define PSR_I_MASK 0x4000
35#define PSR_PK_MASK 0x8000
36
37#define PSR_DT_MASK (1<<17)
38#define PSR_RT_MASK (1<<27)
39
40#define PSR_DFL_MASK (1<<18)
41#define PSR_DFH_MASK (1<<19)
42
43#define PSR_IT_MASK 0x0000001000000000
44
45#define PSR_CPL_SHIFT 32
46#define PSR_CPL_MASK_SHIFTED 3
47
48#define PFM_MASK (~0x3fffffffff)
49
50#define RSC_MODE_MASK 3
51#define RSC_PL_MASK 12
52
53/** Application registers. */
54#define AR_KR0 0
55#define AR_KR1 1
56#define AR_KR2 2
57#define AR_KR3 3
58#define AR_KR4 4
59#define AR_KR5 5
60#define AR_KR6 6
61#define AR_KR7 7
62/* AR 8-15 reserved */
63#define AR_RSC 16
64#define AR_BSP 17
65#define AR_BSPSTORE 18
66#define AR_RNAT 19
67/* AR 20 reserved */
68#define AR_FCR 21
69/* AR 22-23 reserved */
70#define AR_EFLAG 24
71#define AR_CSD 25
72#define AR_SSD 26
73#define AR_CFLG 27
74#define AR_FSR 28
75#define AR_FIR 29
76#define AR_FDR 30
77/* AR 31 reserved */
78#define AR_CCV 32
79/* AR 33-35 reserved */
80#define AR_UNAT 36
81/* AR 37-39 reserved */
82#define AR_FPSR 40
83/* AR 41-43 reserved */
84#define AR_ITC 44
85/* AR 45-47 reserved */
86/* AR 48-63 ignored */
87#define AR_PFS 64
88#define AR_LC 65
89#define AR_EC 66
90/* AR 67-111 reserved */
91/* AR 112-127 ignored */
92
93/** Control registers. */
94#define CR_DCR 0
95#define CR_ITM 1
96#define CR_IVA 2
97/* CR3-CR7 reserved */
98#define CR_PTA 8
99/* CR9-CR15 reserved */
100#define CR_IPSR 16
101#define CR_ISR 17
102/* CR18 reserved */
103#define CR_IIP 19
104#define CR_IFA 20
105#define CR_ITIR 21
106#define CR_IIPA 22
107#define CR_IFS 23
108#define CR_IIM 24
109#define CR_IHA 25
110/* CR26-CR63 reserved */
111#define CR_LID 64
112#define CR_IVR 65
113#define CR_TPR 66
114#define CR_EOI 67
115#define CR_IRR0 68
116#define CR_IRR1 69
117#define CR_IRR2 70
118#define CR_IRR3 71
119#define CR_ITV 72
120#define CR_PMV 73
121#define CR_CMCV 74
122/* CR75-CR79 reserved */
123#define CR_LRR0 80
124#define CR_LRR1 81
125/* CR82-CR127 reserved */
126
127#ifndef __ASM__
128
129#include <arch/types.h>
130
131/** Processor Status Register. */
132union psr {
133 __u64 value;
134 struct {
135 unsigned : 1;
136 unsigned be : 1; /**< Big-Endian data accesses. */
137 unsigned up : 1; /**< User Performance monitor enable. */
138 unsigned ac : 1; /**< Alignment Check. */
139 unsigned mfl : 1; /**< Lower floating-point register written. */
140 unsigned mfh : 1; /**< Upper floating-point register written. */
141 unsigned : 7;
142 unsigned ic : 1; /**< Interruption Collection. */
143 unsigned i : 1; /**< Interrupt Bit. */
144 unsigned pk : 1; /**< Protection Key enable. */
145 unsigned : 1;
146 unsigned dt : 1; /**< Data address Translation. */
147 unsigned dfl : 1; /**< Disabled Floating-point Low register set. */
148 unsigned dfh : 1; /**< Disabled Floating-point High register set. */
149 unsigned sp : 1; /**< Secure Performance monitors. */
150 unsigned pp : 1; /**< Privileged Performance monitor enable. */
151 unsigned di : 1; /**< Disable Instruction set transition. */
152 unsigned si : 1; /**< Secure Interval timer. */
153 unsigned db : 1; /**< Debug Breakpoint fault. */
154 unsigned lp : 1; /**< Lower Privilege transfer trap. */
155 unsigned tb : 1; /**< Taken Branch trap. */
156 unsigned rt : 1; /**< Register Stack Translation. */
157 unsigned : 4;
158 unsigned cpl : 2; /**< Current Privilege Level. */
159 unsigned is : 1; /**< Instruction Set. */
160 unsigned mc : 1; /**< Machine Check abort mask. */
161 unsigned it : 1; /**< Instruction address Translation. */
162 unsigned id : 1; /**< Instruction Debug fault disable. */
163 unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */
164 unsigned dd : 1; /**< Data Debug fault disable. */
165 unsigned ss : 1; /**< Single Step enable. */
166 unsigned ri : 2; /**< Restart Instruction. */
167 unsigned ed : 1; /**< Exception Deferral. */
168 unsigned bn : 1; /**< Register Bank. */
169 unsigned ia : 1; /**< Disable Instruction Access-bit faults. */
170 } __attribute__ ((packed));
171};
172typedef union psr psr_t;
173
174/** Register Stack Configuration Register */
175union rsc {
176 __u64 value;
177 struct {
178 unsigned mode : 2;
179 unsigned pl : 2; /**< Privilege Level. */
180 unsigned be : 1; /**< Big-endian. */
181 unsigned : 11;
182 unsigned loadrs : 14;
183 } __attribute__ ((packed));
184};
185typedef union rsc rsc_t;
186
187/** External Interrupt Vector Register */
188union cr_ivr {
189 __u8 vector;
190 __u64 value;
191};
192
193typedef union cr_ivr cr_ivr_t;
194
195/** Task Priority Register */
196union cr_tpr {
197 struct {
198 unsigned : 4;
199 unsigned mic: 4; /**< Mask Interrupt Class. */
200 unsigned : 8;
201 unsigned mmi: 1; /**< Mask Maskable Interrupts. */
202 } __attribute__ ((packed));
203 __u64 value;
204};
205
206typedef union cr_tpr cr_tpr_t;
207
208/** Interval Timer Vector */
209union cr_itv {
210 struct {
211 unsigned vector : 8;
212 unsigned : 4;
213 unsigned : 1;
214 unsigned : 3;
215 unsigned m : 1; /**< Mask. */
216 } __attribute__ ((packed));
217 __u64 value;
218};
219
220typedef union cr_itv cr_itv_t;
221
222/** Interruption Status Register */
223union cr_isr {
224 struct {
225 union {
226 /** General Exception code field structuring. */
227 struct {
228 unsigned ge_na : 4;
229 unsigned ge_code : 4;
230 } __attribute__ ((packed));
231 __u16 code;
232 };
233 __u8 vector;
234 unsigned : 8;
235 unsigned x : 1; /**< Execute exception. */
236 unsigned w : 1; /**< Write exception. */
237 unsigned r : 1; /**< Read exception. */
238 unsigned na : 1; /**< Non-access exception. */
239 unsigned sp : 1; /**< Speculative load exception. */
240 unsigned rs : 1; /**< Register stack. */
241 unsigned ir : 1; /**< Incomplete Register frame. */
242 unsigned ni : 1; /**< Nested Interruption. */
243 unsigned so : 1; /**< IA-32 Supervisor Override. */
244 unsigned ei : 2; /**< Excepting Instruction. */
245 unsigned ed : 1; /**< Exception Deferral. */
246 unsigned : 20;
247 } __attribute__ ((packed));
248 __u64 value;
249};
250
251typedef union cr_isr cr_isr_t;
252
253/** CPUID Register 3 */
254union cpuid3 {
255 struct {
256 __u8 number;
257 __u8 revision;
258 __u8 model;
259 __u8 family;
260 __u8 archrev;
261 } __attribute__ ((packed));
262 __u64 value;
263};
264
265typedef union cpuid3 cpuid3_t;
266
267#endif /* !__ASM__ */
268
269#endif
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