source: mainline/arch/ia64/include/mm/tlb.h@ 50fe620

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 50fe620 was 25d7709, checked in by Jakub Jermar <jakub@…>, 20 years ago

Nicer ia32 interrupt handlers and structures holding interrupted context data.
Unify the name holding interrupted context data on all architectures to be istate.

  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ia64_TLB_H__
30#define __ia64_TLB_H__
31
32#define tlb_arch_init()
33#define tlb_print()
34
35#include <arch/mm/page.h>
36#include <arch/mm/asid.h>
37#include <arch/interrupt.h>
38#include <arch/types.h>
39#include <typedefs.h>
40
41/** Data and instruction Translation Register indices. */
42#define DTR_KERNEL 0
43#define ITR_KERNEL 0
44#define DTR_KSTACK 1
45
46/** Portion of TLB insertion format data structure. */
47union tlb_entry {
48 __u64 word[2];
49 struct {
50 /* Word 0 */
51 unsigned p : 1; /**< Present. */
52 unsigned : 1;
53 unsigned ma : 3; /**< Memory attribute. */
54 unsigned a : 1; /**< Accessed. */
55 unsigned d : 1; /**< Dirty. */
56 unsigned pl : 2; /**< Privilege level. */
57 unsigned ar : 3; /**< Access rights. */
58 unsigned long long ppn : 38; /**< Physical Page Number, a.k.a. PFN. */
59 unsigned : 2;
60 unsigned ed : 1;
61 unsigned ig1 : 11;
62
63 /* Word 1 */
64 unsigned : 2;
65 unsigned ps : 6; /**< Page size will be 2^ps. */
66 unsigned key : 24; /**< Protection key, unused. */
67 unsigned : 32;
68 } __attribute__ ((packed));
69} __attribute__ ((packed));
70typedef union tlb_entry tlb_entry_t;
71
72extern void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc);
73extern void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
74extern void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
75
76extern void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr);
77extern void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
78extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
79
80extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
81
82extern void dtc_pte_copy(pte_t *t);
83extern void itc_pte_copy(pte_t *t);
84
85extern void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate);
86extern void alternate_data_tlb_fault(__u64 vector, istate_t *istate);
87extern void data_nested_tlb_fault(__u64 vector, istate_t *istate);
88extern void data_dirty_bit_fault(__u64 vector, istate_t *istate);
89extern void instruction_access_bit_fault(__u64 vector, istate_t *istate);
90extern void data_access_bit_fault(__u64 vector, istate_t *istate);
91extern void page_not_present(__u64 vector, istate_t *istate);
92
93#endif
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