source: mainline/arch/ia64/include/mm/page.h@ 208259c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 208259c was 68091bd, checked in by Jakub Vana <jakub.vana@…>, 20 years ago

Incomplete VHPT walker support for Itanium
  • Property mode set to 100644
File size: 6.3 KB
Line 
1/*
2 * Copyright (C) 2005 - 2006 Jakub Jermar
3 * Copyright (C) 2006 Jakub Vana
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __ia64_PAGE_H__
31#define __ia64_PAGE_H__
32
33#include <arch/mm/frame.h>
34
35#define PAGE_SIZE FRAME_SIZE
36#define PAGE_WIDTH FRAME_WIDTH
37
38
39#ifdef KERNEL
40
41/** Bit width of the TLB-locked portion of kernel address space. */
42#define KERNEL_PAGE_WIDTH 28 /* 256M */
43
44#define PPN_SHIFT 12
45
46#define VRN_SHIFT 61
47#define VRN_MASK (7LL << VRN_SHIFT)
48#define VA2VRN(va) ((va)>>VRN_SHIFT)
49
50#ifdef __ASM__
51#define VRN_KERNEL 7
52#else
53#define VRN_KERNEL 7LL
54#endif
55
56#define REGION_REGISTERS 8
57
58#define KA2PA(x) ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
59#define PA2KA(x) ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
60
61#define VHPT_WIDTH 20 /* 1M */
62#define VHPT_SIZE (1 << VHPT_WIDTH)
63
64#define PTA_BASE_SHIFT 15
65
66/** Memory Attributes. */
67#define MA_WRITEBACK 0x0
68#define MA_UNCACHEABLE 0x4
69
70/** Privilege Levels. Only the most and the least privileged ones are ever used. */
71#define PL_KERNEL 0x0
72#define PL_USER 0x3
73
74/* Access Rigths. Only certain combinations are used by the kernel. */
75#define AR_READ 0x0
76#define AR_EXECUTE 0x1
77#define AR_WRITE 0x2
78
79#ifndef __ASM__
80
81#include <arch/mm/frame.h>
82#include <arch/barrier.h>
83#include <genarch/mm/page_ht.h>
84#include <arch/mm/asid.h>
85#include <arch/types.h>
86#include <typedefs.h>
87#include <debug.h>
88
89struct vhpt_tag_info {
90 unsigned long long tag : 63;
91 unsigned ti : 1;
92} __attribute__ ((packed));
93
94union vhpt_tag {
95 struct vhpt_tag_info tag_info;
96 unsigned tag_word;
97};
98
99struct vhpt_entry_present {
100 /* Word 0 */
101 unsigned p : 1;
102 unsigned : 1;
103 unsigned ma : 3;
104 unsigned a : 1;
105 unsigned d : 1;
106 unsigned pl : 2;
107 unsigned ar : 3;
108 unsigned long long ppn : 38;
109 unsigned : 2;
110 unsigned ed : 1;
111 unsigned ig1 : 11;
112
113 /* Word 1 */
114 unsigned : 2;
115 unsigned ps : 6;
116 unsigned key : 24;
117 unsigned : 32;
118
119 /* Word 2 */
120 union vhpt_tag tag;
121
122 /* Word 3 */
123 __u64 ig3 : 64;
124} __attribute__ ((packed));
125
126struct vhpt_entry_not_present {
127 /* Word 0 */
128 unsigned p : 1;
129 unsigned long long ig0 : 52;
130 unsigned ig1 : 11;
131
132 /* Word 1 */
133 unsigned : 2;
134 unsigned ps : 6;
135 unsigned long long ig2 : 56;
136
137 /* Word 2 */
138 union vhpt_tag tag;
139
140 /* Word 3 */
141 __u64 ig3 : 64;
142} __attribute__ ((packed));
143
144typedef union vhpt_entry {
145 struct vhpt_entry_present present;
146 struct vhpt_entry_not_present not_present;
147 __u64 word[4];
148} vhpt_entry_t;
149
150struct region_register_map {
151 unsigned ve : 1;
152 unsigned : 1;
153 unsigned ps : 6;
154 unsigned rid : 24;
155 unsigned : 32;
156} __attribute__ ((packed));
157
158typedef union region_register {
159 struct region_register_map map;
160 unsigned long long word;
161} region_register;
162
163struct pta_register_map {
164 unsigned ve : 1;
165 unsigned : 1;
166 unsigned size : 6;
167 unsigned vf : 1;
168 unsigned : 6;
169 unsigned long long base : 49;
170} __attribute__ ((packed));
171
172typedef union pta_register {
173 struct pta_register_map map;
174 __u64 word;
175} pta_register;
176
177/** Return Translation Hashed Entry Address.
178 *
179 * VRN bits are used to read RID (ASID) from one
180 * of the eight region registers registers.
181 *
182 * @param va Virtual address including VRN bits.
183 *
184 * @return Address of the head of VHPT collision chain.
185 */
186static inline __u64 thash(__u64 va)
187{
188 __u64 ret;
189
190 __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
191
192 return ret;
193}
194
195/** Return Translation Hashed Entry Tag.
196 *
197 * VRN bits are used to read RID (ASID) from one
198 * of the eight region registers.
199 *
200 * @param va Virtual address including VRN bits.
201 *
202 * @return The unique tag for VPN and RID in the collision chain returned by thash().
203 */
204static inline __u64 ttag(__u64 va)
205{
206 __u64 ret;
207
208 __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
209
210 return ret;
211}
212
213/** Read Region Register.
214 *
215 * @param i Region register index.
216 *
217 * @return Current contents of rr[i].
218 */
219static inline __u64 rr_read(index_t i)
220{
221 __u64 ret;
222 ASSERT(i < REGION_REGISTERS);
223 __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
224 return ret;
225}
226
227/** Write Region Register.
228 *
229 * @param i Region register index.
230 * @param v Value to be written to rr[i].
231 */
232static inline void rr_write(index_t i, __u64 v)
233{
234 ASSERT(i < REGION_REGISTERS);
235 __asm__ volatile (
236 "mov rr[%0] = %1\n"
237 :
238 : "r" (i << VRN_SHIFT), "r" (v)
239 );
240}
241
242/** Read Page Table Register.
243 *
244 * @return Current value stored in PTA.
245 */
246static inline __u64 pta_read(void)
247{
248 __u64 ret;
249
250 __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
251
252 return ret;
253}
254
255/** Write Page Table Register.
256 *
257 * @param v New value to be stored in PTA.
258 */
259static inline void pta_write(__u64 v)
260{
261 __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
262}
263
264extern void page_arch_init(void);
265
266extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
267extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
268extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
269
270#endif /* __ASM__ */
271
272#endif /* KERNEL */
273
274#endif
Note: See TracBrowser for help on using the repository browser.