source: mainline/arch/ia64/include/interrupt.h@ 69f293e

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 69f293e was 41fa6f2, checked in by Jakub Vana <jakub.vana@…>, 20 years ago

Itanium FPU Lazy context switching… but not so much tested

  • Property mode set to 100644
File size: 3.1 KB
RevLine 
[dbd1059]1/*
2 * Copyright (C) 2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ia64_INTERRUPT_H__
30#define __ia64_INTERRUPT_H__
31
[25d7709]32#include <typedefs.h>
[e2ec980f]33#include <arch/types.h>
[2ccd275]34#include <arch/register.h>
[e2ec980f]35
[2ccd275]36/** External Interrupt vectors. */
[05d9dd89]37#define INTERRUPT_TIMER 0
38#define INTERRUPT_SPURIOUS 15
39
[2ccd275]40/** General Exception codes. */
41#define GE_ILLEGALOP 0
42#define GE_PRIVOP 1
43#define GE_PRIVREG 2
44#define GE_RESREGFLD 3
45#define GE_DISBLDISTRAN 4
46#define GE_ILLEGALDEP 8
47
[154049e]48#define EOI 0 /**< The actual value doesn't matter. */
49
[25d7709]50struct istate {
[41fa6f2]51
52 __r128 f2;
53 __r128 f3;
54 __r128 f4;
55 __r128 f5;
56 __r128 f6;
57 __r128 f7;
58 __r128 f8;
59 __r128 f9;
60 __r128 f10;
61 __r128 f11;
62 __r128 f12;
63 __r128 f13;
64 __r128 f14;
65 __r128 f15;
66 __r128 f16;
67 __r128 f17;
68 __r128 f18;
69 __r128 f19;
70 __r128 f20;
71 __r128 f21;
72 __r128 f22;
73 __r128 f23;
74 __r128 f24;
75 __r128 f25;
76 __r128 f26;
77 __r128 f27;
78 __r128 f28;
79 __r128 f29;
80 __r128 f30;
81 __r128 f31;
82
83
[e2ec980f]84 __address ar_bsp;
85 __address ar_bspstore;
[e1c68e0c]86 __address ar_bspstore_new;
[e2ec980f]87 __u64 ar_rnat;
88 __u64 ar_ifs;
89 __u64 ar_pfs;
90 __u64 ar_rsc;
91 __address cr_ifa;
[2ccd275]92 cr_isr_t cr_isr;
[e2ec980f]93 __address cr_iipa;
[901122b]94 psr_t cr_ipsr;
[e2ec980f]95 __address cr_iip;
96 __u64 pr;
[83d2d0e]97 __address sp;
[901122b]98
99 /*
100 * The following variables are defined only for break_instruction handler.
101 */
102 __u64 in0;
103 __u64 in1;
104 __u64 in2;
105 __u64 in3;
[5c089c3a]106 __u64 in4;
[1065603e]107};
[e2ec980f]108
109extern void *ivt;
110
[25d7709]111extern void general_exception(__u64 vector, istate_t *istate);
112extern int break_instruction(__u64 vector, istate_t *istate);
113extern void universal_handler(__u64 vector, istate_t *istate);
[9e1c942]114extern void nop_handler(__u64 vector, istate_t *istate);
[25d7709]115extern void external_interrupt(__u64 vector, istate_t *istate);
[9e1c942]116extern void disabled_fp_register(__u64 vector, istate_t *istate);
117
118
[dbd1059]119
120#endif
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