source: mainline/arch/ia32/src/smp/mps.c@ 2c457e8

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2c457e8 was 84dd253, checked in by Jakub Jermar <jakub@…>, 20 years ago

Physical memory management work.
New frame allocator.
Some architectures need to have bigger heap.
  • Property mode set to 100644
File size: 10.1 KB
Line 
1/*
2 * Copyright (C) 2001-2005 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifdef __SMP__
30
31#include <config.h>
32#include <print.h>
33#include <debug.h>
34#include <arch/smp/mps.h>
35#include <arch/smp/apic.h>
36#include <arch/smp/smp.h>
37#include <func.h>
38#include <arch/types.h>
39#include <typedefs.h>
40#include <cpu.h>
41#include <arch/asm.h>
42#include <arch/bios/bios.h>
43#include <mm/frame.h>
44
45/*
46 * MultiProcessor Specification detection code.
47 */
48
49#define FS_SIGNATURE 0x5f504d5f
50#define CT_SIGNATURE 0x504d4350
51
52int mps_fs_check(__u8 *base);
53int mps_ct_check(void);
54
55int configure_via_ct(void);
56int configure_via_default(__u8 n);
57
58int ct_processor_entry(struct __processor_entry *pr);
59void ct_bus_entry(struct __bus_entry *bus);
60void ct_io_apic_entry(struct __io_apic_entry *ioa);
61void ct_io_intr_entry(struct __io_intr_entry *iointr);
62void ct_l_intr_entry(struct __l_intr_entry *lintr);
63
64void ct_extended_entries(void);
65
66static struct mps_fs *fs;
67static struct mps_ct *ct;
68
69struct __processor_entry *processor_entries = NULL;
70struct __bus_entry *bus_entries = NULL;
71struct __io_apic_entry *io_apic_entries = NULL;
72struct __io_intr_entry *io_intr_entries = NULL;
73struct __l_intr_entry *l_intr_entries = NULL;
74
75int processor_entry_cnt = 0;
76int bus_entry_cnt = 0;
77int io_apic_entry_cnt = 0;
78int io_intr_entry_cnt = 0;
79int l_intr_entry_cnt = 0;
80
81waitq_t ap_completion_wq;
82waitq_t kmp_completion_wq;
83
84
85/*
86 * Implementation of IA-32 SMP configuration interface.
87 */
88static count_t get_cpu_count(void);
89static bool is_cpu_enabled(index_t i);
90static bool is_bsp(index_t i);
91static __u8 get_cpu_apic_id(index_t i);
92
93struct smp_config_operations mps_config_operations = {
94 .cpu_count = get_cpu_count,
95 .cpu_enabled = is_cpu_enabled,
96 .cpu_bootstrap = is_bsp,
97 .cpu_apic_id = get_cpu_apic_id
98};
99
100count_t get_cpu_count(void)
101{
102 return processor_entry_cnt;
103}
104
105bool is_cpu_enabled(index_t i)
106{
107 ASSERT(i < processor_entry_cnt);
108 return processor_entries[i].cpu_flags & 0x1;
109}
110
111bool is_bsp(index_t i)
112{
113 ASSERT(i < processor_entry_cnt);
114 return processor_entries[i].cpu_flags & 0x2;
115}
116
117__u8 get_cpu_apic_id(index_t i)
118{
119 ASSERT(i < processor_entry_cnt);
120 return processor_entries[i].l_apic_id;
121}
122
123
124/*
125 * Used to check the integrity of the MP Floating Structure.
126 */
127int mps_fs_check(__u8 *base)
128{
129 int i;
130 __u8 sum;
131
132 for (i = 0, sum = 0; i < 16; i++)
133 sum += base[i];
134
135 return !sum;
136}
137
138/*
139 * Used to check the integrity of the MP Configuration Table.
140 */
141int mps_ct_check(void)
142{
143 __u8 *base = (__u8 *) ct;
144 __u8 *ext = base + ct->base_table_length;
145 __u8 sum;
146 int i;
147
148 /* count the checksum for the base table */
149 for (i=0,sum=0; i < ct->base_table_length; i++)
150 sum += base[i];
151
152 if (sum)
153 return 0;
154
155 /* count the checksum for the extended table */
156 for (i=0,sum=0; i < ct->ext_table_length; i++)
157 sum += ext[i];
158
159 return sum == ct->ext_table_checksum;
160}
161
162void mps_init(void)
163{
164 __u8 *addr[2] = { NULL, (__u8 *) PA2KA(0xf0000) };
165 int i, j, length[2] = { 1024, 64*1024 };
166
167
168 /*
169 * Find MP Floating Pointer Structure
170 * 1a. search first 1K of EBDA
171 * 1b. if EBDA is undefined, search last 1K of base memory
172 * 2. search 64K starting at 0xf0000
173 */
174
175 addr[0] = (__u8 *) PA2KA(ebda ? ebda : 639 * 1024);
176 for (i = 0; i < 2; i++) {
177 for (j = 0; j < length[i]; j += 16) {
178 if (*((__u32 *) &addr[i][j]) == FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
179 fs = (struct mps_fs *) &addr[i][j];
180 goto fs_found;
181 }
182 }
183 }
184
185 return;
186
187fs_found:
188 printf("%P: MPS Floating Pointer Structure\n", fs);
189
190 if (fs->config_type == 0 && fs->configuration_table) {
191 if (fs->mpfib2 >> 7) {
192 printf("%s: PIC mode not supported\n", __FUNCTION__);
193 return;
194 }
195
196 ct = (struct mps_ct *)PA2KA((__address)fs->configuration_table);
197 config.cpu_count = configure_via_ct();
198 }
199 else
200 config.cpu_count = configure_via_default(fs->config_type);
201
202 return;
203}
204
205int configure_via_ct(void)
206{
207 __u8 *cur;
208 int i, cnt;
209
210 if (ct->signature != CT_SIGNATURE) {
211 printf("%s: bad ct->signature\n", __FUNCTION__);
212 return 1;
213 }
214 if (!mps_ct_check()) {
215 printf("%s: bad ct checksum\n", __FUNCTION__);
216 return 1;
217 }
218 if (ct->oem_table) {
219 printf("%s: ct->oem_table not supported\n", __FUNCTION__);
220 return 1;
221 }
222
223 l_apic = (__u32 *)(__address)ct->l_apic;
224
225 cnt = 0;
226 cur = &ct->base_table[0];
227 for (i=0; i < ct->entry_count; i++) {
228 switch (*cur) {
229 /* Processor entry */
230 case 0:
231 processor_entries = processor_entries ? processor_entries : (struct __processor_entry *) cur;
232 processor_entry_cnt++;
233 cnt += ct_processor_entry((struct __processor_entry *) cur);
234 cur += 20;
235 break;
236
237 /* Bus entry */
238 case 1:
239 bus_entries = bus_entries ? bus_entries : (struct __bus_entry *) cur;
240 bus_entry_cnt++;
241 ct_bus_entry((struct __bus_entry *) cur);
242 cur += 8;
243 break;
244
245 /* I/O Apic */
246 case 2:
247 io_apic_entries = io_apic_entries ? io_apic_entries : (struct __io_apic_entry *) cur;
248 io_apic_entry_cnt++;
249 ct_io_apic_entry((struct __io_apic_entry *) cur);
250 cur += 8;
251 break;
252
253 /* I/O Interrupt Assignment */
254 case 3:
255 io_intr_entries = io_intr_entries ? io_intr_entries : (struct __io_intr_entry *) cur;
256 io_intr_entry_cnt++;
257 ct_io_intr_entry((struct __io_intr_entry *) cur);
258 cur += 8;
259 break;
260
261 /* Local Interrupt Assignment */
262 case 4:
263 l_intr_entries = l_intr_entries ? l_intr_entries : (struct __l_intr_entry *) cur;
264 l_intr_entry_cnt++;
265 ct_l_intr_entry((struct __l_intr_entry *) cur);
266 cur += 8;
267 break;
268
269 default:
270 /*
271 * Something is wrong. Fallback to UP mode.
272 */
273
274 printf("%s: ct badness\n", __FUNCTION__);
275 return 1;
276 }
277 }
278
279 /*
280 * Process extended entries.
281 */
282 ct_extended_entries();
283 return cnt;
284}
285
286int configure_via_default(__u8 n)
287{
288 /*
289 * Not yet implemented.
290 */
291 printf("%s: not supported\n", __FUNCTION__);
292 return 1;
293}
294
295
296int ct_processor_entry(struct __processor_entry *pr)
297{
298 /*
299 * Ignore processors which are not marked enabled.
300 */
301 if ((pr->cpu_flags & (1<<0)) == 0)
302 return 0;
303
304 apic_id_mask |= (1<<pr->l_apic_id);
305 return 1;
306}
307
308void ct_bus_entry(struct __bus_entry *bus)
309{
310#ifdef MPSCT_VERBOSE
311 char buf[7];
312 memcpy((void *) buf, (void *) bus->bus_type, 6);
313 buf[6] = 0;
314 printf("bus%d: %s\n", bus->bus_id, buf);
315#endif
316}
317
318void ct_io_apic_entry(struct __io_apic_entry *ioa)
319{
320 static int io_apic_count = 0;
321
322 /* this ioapic is marked unusable */
323 if (ioa->io_apic_flags & 1 == 0)
324 return;
325
326 if (io_apic_count++ > 0) {
327 /*
328 * Multiple IO APIC's are currently not supported.
329 */
330 return;
331 }
332
333 io_apic = (__u32 *)(__address)ioa->io_apic;
334}
335
336//#define MPSCT_VERBOSE
337void ct_io_intr_entry(struct __io_intr_entry *iointr)
338{
339#ifdef MPSCT_VERBOSE
340 switch (iointr->intr_type) {
341 case 0: printf("INT"); break;
342 case 1: printf("NMI"); break;
343 case 2: printf("SMI"); break;
344 case 3: printf("ExtINT"); break;
345 }
346 putchar(',');
347 switch (iointr->poel&3) {
348 case 0: printf("bus-like"); break;
349 case 1: printf("active high"); break;
350 case 2: printf("reserved"); break;
351 case 3: printf("active low"); break;
352 }
353 putchar(',');
354 switch ((iointr->poel>>2)&3) {
355 case 0: printf("bus-like"); break;
356 case 1: printf("edge-triggered"); break;
357 case 2: printf("reserved"); break;
358 case 3: printf("level-triggered"); break;
359 }
360 putchar(',');
361 printf("bus%d,irq%d", iointr->src_bus_id, iointr->src_bus_irq);
362 putchar(',');
363 printf("io_apic%d,pin%d", iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
364 putchar('\n');
365#endif
366}
367
368void ct_l_intr_entry(struct __l_intr_entry *lintr)
369{
370#ifdef MPSCT_VERBOSE
371 switch (lintr->intr_type) {
372 case 0: printf("INT"); break;
373 case 1: printf("NMI"); break;
374 case 2: printf("SMI"); break;
375 case 3: printf("ExtINT"); break;
376 }
377 putchar(',');
378 switch (lintr->poel&3) {
379 case 0: printf("bus-like"); break;
380 case 1: printf("active high"); break;
381 case 2: printf("reserved"); break;
382 case 3: printf("active low"); break;
383 }
384 putchar(',');
385 switch ((lintr->poel>>2)&3) {
386 case 0: printf("bus-like"); break;
387 case 1: printf("edge-triggered"); break;
388 case 2: printf("reserved"); break;
389 case 3: printf("level-triggered"); break;
390 }
391 putchar(',');
392 printf("bus%d,irq%d", lintr->src_bus_id, lintr->src_bus_irq);
393 putchar(',');
394 printf("l_apic%d,pin%d", lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
395 putchar('\n');
396#endif
397}
398
399void ct_extended_entries(void)
400{
401 __u8 *ext = (__u8 *) ct + ct->base_table_length;
402 __u8 *cur;
403
404 for (cur = ext; cur < ext + ct->ext_table_length; cur += cur[CT_EXT_ENTRY_LEN]) {
405 switch (cur[CT_EXT_ENTRY_TYPE]) {
406 default:
407 printf("%P: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
408 break;
409 }
410 }
411}
412
413int mps_irq_to_pin(int irq)
414{
415 int i;
416
417 for(i=0;i<io_intr_entry_cnt;i++) {
418 if (io_intr_entries[i].src_bus_irq == irq && io_intr_entries[i].intr_type == 0)
419 return io_intr_entries[i].dst_io_apic_pin;
420 }
421
422 return -1;
423}
424
425#endif /* __SMP__ */
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