source: mainline/arch/ia32/src/smp/apic.c@ 5f85c91

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5f85c91 was 5f85c91, checked in by Martin Decky <martin@…>, 20 years ago

make configuration variables usage consistent
  • Property mode set to 100644
File size: 10.2 KB
RevLine 
[f761f1eb]1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/types.h>
[397c77f]30#include <arch/smp/apic.h>
31#include <arch/smp/ap.h>
[ed0dd65]32#include <arch/smp/mps.h>
[f761f1eb]33#include <mm/page.h>
34#include <time/delay.h>
35#include <arch/interrupt.h>
36#include <print.h>
37#include <arch/asm.h>
38#include <arch.h>
39
[5f85c91]40#ifdef CONFIG_SMP
[8262010]41
[f761f1eb]42/*
43 * This is functional, far-from-general-enough interface to the APIC.
44 * Advanced Programmable Interrupt Controller for MP systems.
45 * Tested on:
[b0bf501]46 * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
[87cd61f]47 * Simics 2.0.28 - Simics 2.2.14 2-4 CPUs
[f761f1eb]48 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
[2c457e8]49 * ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
50 * MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
[f761f1eb]51 */
52
53/*
54 * These variables either stay configured as initilalized, or are changed by
55 * the MP configuration code.
56 *
57 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
58 * optimize the code too much and accesses to l_apic and io_apic, that must
59 * always be 32-bit, would use byte oriented instructions.
60 */
61volatile __u32 *l_apic = (__u32 *) 0xfee00000;
62volatile __u32 *io_apic = (__u32 *) 0xfec00000;
63
64__u32 apic_id_mask = 0;
65
66int apic_poll_errors(void);
67
68void apic_init(void)
69{
70 __u32 tmp, id, i;
71
72 trap_register(VECTOR_APIC_SPUR, apic_spurious);
73
74 enable_irqs_function = io_apic_enable_irqs;
75 disable_irqs_function = io_apic_disable_irqs;
76 eoi_function = l_apic_eoi;
77
78 /*
79 * Configure interrupt routing.
80 * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
81 * Other interrupts will be forwarded to the lowest priority CPU.
82 */
83 io_apic_disable_irqs(0xffff);
84 trap_register(VECTOR_CLK, l_apic_timer_interrupt);
85 for (i=1; i<16; i++) {
86 int pin;
87
[ed0dd65]88 if ((pin = mps_irq_to_pin(i)) != -1)
[76cec1e]89 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
[f761f1eb]90 }
91
92
93 /*
94 * Ensure that io_apic has unique ID.
95 */
96 tmp = io_apic_read(IOAPICID);
97 id = (tmp >> 24) & 0xf;
98 if ((1<<id) & apic_id_mask) {
99 int i;
100
101 for (i=0; i<15; i++) {
102 if (!((1<<i) & apic_id_mask)) {
103 io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
104 break;
105 }
106 }
107 }
108
109 /*
110 * Configure the BSP's lapic.
111 */
112 l_apic_init();
113 l_apic_debug();
114}
115
[ab08b42]116void apic_spurious(__u8 n, __native stack[])
[f761f1eb]117{
[43114c5]118 printf("cpu%d: APIC spurious interrupt\n", CPU->id);
[f761f1eb]119}
120
121int apic_poll_errors(void)
122{
123 __u32 esr;
124
125 esr = l_apic[ESR] & ~ESRClear;
126
127 if ((esr>>0) & 1)
128 printf("Send CS Error\n");
129 if ((esr>>1) & 1)
130 printf("Receive CS Error\n");
131 if ((esr>>2) & 1)
132 printf("Send Accept Error\n");
133 if ((esr>>3) & 1)
134 printf("Receive Accept Error\n");
135 if ((esr>>5) & 1)
136 printf("Send Illegal Vector\n");
137 if ((esr>>6) & 1)
138 printf("Received Illegal Vector\n");
139 if ((esr>>7) & 1)
140 printf("Illegal Register Address\n");
[76cec1e]141
[f761f1eb]142 return !esr;
143}
144
[169587a]145/*
[43114c5]146 * Send all CPUs excluding CPU IPI vector.
[169587a]147 */
148int l_apic_broadcast_custom_ipi(__u8 vector)
149{
150 __u32 lo;
151
152 /*
153 * Read the ICR register in and zero all non-reserved fields.
154 */
155 lo = l_apic[ICRlo] & ICRloClear;
156
157 lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
158
159 l_apic[ICRlo] = lo;
160
161 lo = l_apic[ICRlo] & ICRloClear;
162 if (lo & SEND_PENDING)
163 printf("IPI is pending.\n");
164
165 return apic_poll_errors();
166}
167
[f761f1eb]168/*
169 * Universal Start-up Algorithm for bringing up the AP processors.
170 */
171int l_apic_send_init_ipi(__u8 apicid)
172{
173 __u32 lo, hi;
174 int i;
175
176 /*
177 * Read the ICR register in and zero all non-reserved fields.
178 */
179 lo = l_apic[ICRlo] & ICRloClear;
180 hi = l_apic[ICRhi] & ICRhiClear;
181
182 lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
183 hi |= apicid << 24;
184
185 l_apic[ICRhi] = hi;
186 l_apic[ICRlo] = lo;
[c9b8c5c]187
[f761f1eb]188 /*
189 * According to MP Specification, 20us should be enough to
190 * deliver the IPI.
191 */
192 delay(20);
193
194 if (!apic_poll_errors()) return 0;
195
196 lo = l_apic[ICRlo] & ICRloClear;
197 if (lo & SEND_PENDING)
198 printf("IPI is pending.\n");
[c9b8c5c]199
[f761f1eb]200 l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
201
202 /*
203 * Wait 10ms as MP Specification specifies.
204 */
205 delay(10000);
206
[c9b8c5c]207 if (!is_82489DX_apic(l_apic[LAVR])) {
208 /*
209 * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
210 */
211 for (i = 0; i<2; i++) {
212 lo = l_apic[ICRlo] & ICRloClear;
213 lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
[d47f0e1]214 l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
[c9b8c5c]215 delay(200);
216 }
[f761f1eb]217 }
218
[c9b8c5c]219
[f761f1eb]220 return apic_poll_errors();
221}
222
223void l_apic_init(void)
224{
225 __u32 tmp, t1, t2;
[8262010]226
[f761f1eb]227 l_apic[LVT_Err] |= (1<<16);
228 l_apic[LVT_LINT0] |= (1<<16);
229 l_apic[LVT_LINT1] |= (1<<16);
230
231 tmp = l_apic[SVR] & SVRClear;
232 l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
233
234 l_apic[TPR] &= TPRClear;
235
[434f700]236 if (CPU->arch.family >= 6)
237 enable_l_apic_in_msr();
[f761f1eb]238
239 tmp = l_apic[ICRlo] & ICRloClear;
240 l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
241
242 /*
243 * Program the timer for periodic mode and respective vector.
244 */
245
246 l_apic[TDCR] &= TDCRClear;
247 l_apic[TDCR] |= 0xb;
248 tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
249 l_apic[LVT_Tm] = tmp & ~(1<<16);
250
251 t1 = l_apic[CCRT];
252 l_apic[ICRT] = 0xffffffff;
253
254 while (l_apic[CCRT] == t1)
255 ;
256
257 t1 = l_apic[CCRT];
258 delay(1000);
259 t2 = l_apic[CCRT];
260
261 l_apic[ICRT] = t1-t2;
[434f700]262
[f761f1eb]263}
264
265void l_apic_eoi(void)
266{
267 l_apic[EOI] = 0;
268}
269
270void l_apic_debug(void)
271{
272#ifdef LAPIC_VERBOSE
273 int i, lint;
274
[8262010]275 printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
[f761f1eb]276
277 printf("LVT_Tm: ");
278 if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
279 if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
280 if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
281 printf("%B\n", l_apic[LVT_Tm] & 0xff);
282
283 for (i=0; i<2; i++) {
284 lint = i ? LVT_LINT1 : LVT_LINT0;
285 printf("LVT_LINT%d: ", i);
286 if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
287 if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
288 printf("%d", l_apic[lint] & (1<<14)); putchar(',');
289 printf("%d", l_apic[lint] & (1<<13)); putchar(',');
290 if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
291
292 switch ((l_apic[lint]>>8)&7) {
293 case 0: printf("fixed"); break;
294 case 4: printf("NMI"); break;
295 case 7: printf("ExtINT"); break;
296 }
297 putchar(',');
298 printf("%B\n", l_apic[lint] & 0xff);
299 }
300
301 printf("LVT_Err: ");
302 if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
303 if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
304 printf("%B\n", l_apic[LVT_Err] & 0xff);
305
306 /*
307 * This register is supported only on P6 and higher.
308 */
[8262010]309 if (CPU->arch.family > 5) {
[f761f1eb]310 printf("LVT_PCINT: ");
311 if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
312 if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
313 switch ((l_apic[LVT_PCINT] >> 8)&7) {
314 case 0: printf("fixed"); break;
315 case 4: printf("NMI"); break;
316 case 7: printf("ExtINT"); break;
317 }
318 putchar(',');
319 printf("%B\n", l_apic[LVT_PCINT] & 0xff);
320 }
321#endif
322}
323
[ab08b42]324void l_apic_timer_interrupt(__u8 n, __native stack[])
[f761f1eb]325{
326 l_apic_eoi();
327 clock();
328}
329
[7f1bfce]330__u8 l_apic_id(void)
[8262010]331{
332 return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
333}
334
[f761f1eb]335__u32 io_apic_read(__u8 address)
336{
337 __u32 tmp;
338
339 tmp = io_apic[IOREGSEL] & ~0xf;
340 io_apic[IOREGSEL] = tmp | address;
341 return io_apic[IOWIN];
342}
343
344void io_apic_write(__u8 address, __u32 x)
345{
346 __u32 tmp;
347
348 tmp = io_apic[IOREGSEL] & ~0xf;
349 io_apic[IOREGSEL] = tmp | address;
350 io_apic[IOWIN] = x;
351}
352
353void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
354{
355 __u32 reglo, reghi;
356 int dlvr = 0;
357
358 if (flags & LOPRI)
359 dlvr = 1;
360
361 reglo = io_apic_read(IOREDTBL + signal*2);
362 reghi = io_apic_read(IOREDTBL + signal*2 + 1);
363
364 reghi &= ~0x0f000000;
365 reghi |= (dest<<24);
366
367 reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
368 reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
369
370 io_apic_write(IOREDTBL + signal*2, reglo);
371 io_apic_write(IOREDTBL + signal*2 + 1, reghi);
372}
373
374void io_apic_disable_irqs(__u16 irqmask)
375{
376 int i,pin;
377 __u32 reglo;
378
379 for (i=0;i<16;i++) {
380 if ((irqmask>>i) & 1) {
381 /*
382 * Mask the signal input in IO APIC if there is a
383 * mapping for the respective IRQ number.
384 */
[ed0dd65]385 pin = mps_irq_to_pin(i);
[f761f1eb]386 if (pin != -1) {
387 reglo = io_apic_read(IOREDTBL + pin*2);
388 reglo |= (1<<16);
389 io_apic_write(IOREDTBL + pin*2,reglo);
390 }
391
392 }
393 }
394}
395
396void io_apic_enable_irqs(__u16 irqmask)
397{
398 int i,pin;
399 __u32 reglo;
400
401 for (i=0;i<16;i++) {
402 if ((irqmask>>i) & 1) {
403 /*
404 * Unmask the signal input in IO APIC if there is a
405 * mapping for the respective IRQ number.
406 */
[ed0dd65]407 pin = mps_irq_to_pin(i);
[f761f1eb]408 if (pin != -1) {
409 reglo = io_apic_read(IOREDTBL + pin*2);
410 reglo &= ~(1<<16);
411 io_apic_write(IOREDTBL + pin*2,reglo);
412 }
413
414 }
415 }
416
417}
418
[5f85c91]419#endif /* CONFIG_SMP */
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