source: mainline/arch/ia32/src/interrupt.c@ 51022e9b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 51022e9b was e3b9572, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Interrupts for amd64.

  • Property mode set to 100644
File size: 4.7 KB
RevLine 
[f761f1eb]1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/interrupt.h>
30#include <print.h>
[02a99d2]31#include <debug.h>
[f761f1eb]32#include <panic.h>
33#include <arch/i8259.h>
34#include <func.h>
35#include <cpu.h>
36#include <arch/asm.h>
[169587a]37#include <mm/tlb.h>
[cb4b61d]38#include <arch.h>
[f761f1eb]39
40/*
41 * Interrupt and exception dispatching.
42 */
43
44static iroutine ivt[IVT_ITEMS];
45
46void (* disable_irqs_function)(__u16 irqmask) = NULL;
47void (* enable_irqs_function)(__u16 irqmask) = NULL;
48void (* eoi_function)(void) = NULL;
49
50iroutine trap_register(__u8 n, iroutine f)
51{
[02a99d2]52 ASSERT(n < IVT_ITEMS);
53
[f761f1eb]54 iroutine old;
[02a99d2]55
[f761f1eb]56 old = ivt[n];
57 ivt[n] = f;
[02a99d2]58
59 return old;
[f761f1eb]60}
61
62/*
63 * Called directly from the assembler code.
64 * CPU is cpu_priority_high().
65 */
[c832cc0a]66void trap_dispatcher(__u8 n, __native stack[])
[f761f1eb]67{
[02a99d2]68 ASSERT(n < IVT_ITEMS);
69
70 ivt[n](n, stack);
[f761f1eb]71}
72
[c832cc0a]73void null_interrupt(__u8 n, __native stack[])
[f761f1eb]74{
75 printf("int %d: null_interrupt\n", n);
76 printf("stack: %L, %L, %L, %L\n", stack[0], stack[1], stack[2], stack[3]);
77 panic("unserviced interrupt\n");
78}
79
[c832cc0a]80void gp_fault(__u8 n, __native stack[])
[f761f1eb]81{
[b5eb1ee]82 printf("ERROR_WORD=%X, %%eip=%X, %%cs=%X, flags=%X\n", stack[0], stack[1], stack[2], stack[3]);
[f761f1eb]83 printf("%%eax=%L, %%ebx=%L, %%ecx=%L, %%edx=%L,\n%%edi=%L, %%esi=%L, %%ebp=%L, %%esp=%L\n", stack[-2], stack[-5], stack[-3], stack[-4], stack[-9], stack[-8], stack[-1], stack);
84 printf("stack: %X, %X, %X, %X\n", stack[4], stack[5], stack[6], stack[7]);
[f4a61ef]85 panic("general protection fault\n");
[f761f1eb]86}
87
[c832cc0a]88void ss_fault(__u8 n, __native stack[])
[6de2480e]89{
[b5eb1ee]90 printf("ERROR_WORD=%X, %%eip=%X, %%cs=%X, flags=%X\n", stack[0], stack[1], stack[2], stack[3]);
[6de2480e]91 printf("%%eax=%L, %%ebx=%L, %%ecx=%L, %%edx=%L,\n%%edi=%L, %%esi=%L, %%ebp=%L, %%esp=%L\n", stack[-2], stack[-5], stack[-3], stack[-4], stack[-9], stack[-8], stack[-1], stack);
92 printf("stack: %X, %X, %X, %X\n", stack[4], stack[5], stack[6], stack[7]);
[747a2476]93 panic("stack fault\n");
[6de2480e]94}
95
96
[c832cc0a]97void nm_fault(__u8 n, __native stack[])
[6a27d63]98{
[6de2480e]99 reset_TS_flag();
[76cec1e]100 if ((CPU->fpu_owner)!=NULL) {
101 fpu_lazy_context_save(&((CPU->fpu_owner)->saved_fpu_context));
[54ca3523]102 (CPU->fpu_owner)->fpu_context_engaged=0; /* don't prevent migration */
[6a27d63]103 }
104 if(THREAD->fpu_context_exists) fpu_lazy_context_restore(&(THREAD->saved_fpu_context));
[76cec1e]105 else {fpu_init();THREAD->fpu_context_exists=1;}
[ea3fb2e]106 CPU->fpu_owner=THREAD;
[6a27d63]107}
108
109
110
[c832cc0a]111void page_fault(__u8 n, __native stack[])
[f761f1eb]112{
[18e0a6c]113 printf("page fault address: %X\n", read_cr2());
[b5eb1ee]114 printf("ERROR_WORD=%X, %%eip=%X, %%cs=%X, flags=%X\n", stack[0], stack[1], stack[2], stack[3]);
[f761f1eb]115 printf("%%eax=%L, %%ebx=%L, %%ecx=%L, %%edx=%L,\n%%edi=%L, %%esi=%L, %%ebp=%L, %%esp=%L\n", stack[-2], stack[-5], stack[-3], stack[-4], stack[-9], stack[-8], stack[-1], stack);
116 printf("stack: %X, %X, %X, %X\n", stack[4], stack[5], stack[6], stack[7]);
[87cd61f]117 panic("page fault\n");
[f761f1eb]118}
119
[c832cc0a]120void syscall(__u8 n, __native stack[])
[f761f1eb]121{
[cb4b61d]122 printf("cpu%d: syscall\n", CPU->id);
[434f700]123 thread_usleep(1000);
[f761f1eb]124}
125
[c832cc0a]126void tlb_shootdown_ipi(__u8 n, __native stack[])
[169587a]127{
128 trap_virtual_eoi();
[b109ebb]129 tlb_shootdown_ipi_recv();
[169587a]130}
131
[c832cc0a]132void wakeup_ipi(__u8 n, __native stack[])
[4ffa9e0]133{
134 trap_virtual_eoi();
135}
136
[f761f1eb]137void trap_virtual_enable_irqs(__u16 irqmask)
138{
139 if (enable_irqs_function)
140 enable_irqs_function(irqmask);
141 else
[02a99d2]142 panic("no enable_irqs_function\n");
[f761f1eb]143}
144
145void trap_virtual_disable_irqs(__u16 irqmask)
146{
147 if (disable_irqs_function)
148 disable_irqs_function(irqmask);
149 else
[02a99d2]150 panic("no disable_irqs_function\n");
[f761f1eb]151}
152
153void trap_virtual_eoi(void)
154{
155 if (eoi_function)
156 eoi_function();
157 else
[02a99d2]158 panic("no eoi_function\n");
[f761f1eb]159
160}
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