source: mainline/arch/ia32/src/ia32.c@ 80d31883

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 80d31883 was 80d31883, checked in by Martin Decky <martin@…>, 19 years ago

cleanup

  • Property mode set to 100644
File size: 3.6 KB
RevLine 
[f761f1eb]1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch.h>
30
31#include <arch/types.h>
32#include <typedefs.h>
33
34#include <arch/pm.h>
35
[018f95a]36#include <arch/drivers/ega.h>
[80d31883]37#include <arch/drivers/vesa.h>
[02f441c0]38#include <genarch/i8042/i8042.h>
[80d31883]39#include <arch/drivers/i8254.h>
40#include <arch/drivers/i8259.h>
[f761f1eb]41
42#include <arch/context.h>
43
44#include <config.h>
45
46#include <arch/interrupt.h>
[ad36bd6]47#include <arch/asm.h>
[e16e036a]48#include <genarch/acpi/acpi.h>
[9c0a9b3]49
50#include <arch/bios/bios.h>
51
[1e9a463]52#include <arch/mm/memory_init.h>
[fcfac420]53#include <interrupt.h>
[23d22eb]54#include <arch/debugger.h>
[281b607]55#include <proc/thread.h>
56#include <syscall/syscall.h>
[41d33ac]57#include <console/console.h>
[ad36bd6]58
[f07bba5]59void arch_pre_mm_init(void)
[f761f1eb]60{
61 pm_init();
62
63 if (config.cpu_active == 1) {
[dba84ff]64 bios_init();
[76cec1e]65 i8259_init(); /* PIC */
[f761f1eb]66 i8254_init(); /* hard clock */
[5dce48b9]67
[25d7709]68 exc_register(VECTOR_SYSCALL, "syscall", (iroutine) syscall);
[169587a]69
[5f85c91]70 #ifdef CONFIG_SMP
[fcfac420]71 exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
[25d7709]72 (iroutine) tlb_shootdown_ipi);
[5f85c91]73 #endif /* CONFIG_SMP */
[f761f1eb]74 }
75}
76
[6ba143d]77void arch_post_mm_init(void)
[7eade45]78{
[425913b]79 if (config.cpu_active == 1) {
[22cf454d]80
81#ifdef CONFIG_FB
[381465e]82 if (vesa_present())
83 vesa_init();
[22cf454d]84 else
85#endif
[381465e]86 ega_init(); /* video */
[22cf454d]87
88
[23d22eb]89 /* Enable debugger */
90 debugger_init();
[381465e]91 /* Merge all memory zones to 1 big zone */
92 zone_merge_all();
[babcb148]93 }
94}
95
[7453929]96void arch_pre_smp_init(void)
[babcb148]97{
98 if (config.cpu_active == 1) {
[1e9a463]99 memory_print_map();
100
[5f85c91]101 #ifdef CONFIG_SMP
[85bfdcc8]102 acpi_init();
[5f85c91]103 #endif /* CONFIG_SMP */
[425913b]104 }
[7eade45]105}
106
[7453929]107void arch_post_smp_init(void)
108{
[a83a802]109 i8042_init(); /* keyboard controller */
[7453929]110}
111
[f761f1eb]112void calibrate_delay_loop(void)
113{
114 i8254_calibrate_delay_loop();
[f701b236]115 if (config.cpu_active == 1) {
116 /*
117 * This has to be done only on UP.
118 * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
119 */
120 i8254_normal_operation();
121 }
[f761f1eb]122}
[281b607]123
[e1be3b6]124/** Set thread-local-storage pointer
[281b607]125 *
[3b712407]126 * TLS pointer is set in GS register. That means, the GS contains
127 * selector, and the descriptor->base is the correct address.
[281b607]128 */
129__native sys_tls_set(__native addr)
130{
[a6d4ceb]131 THREAD->arch.tls = addr;
[281b607]132 set_tls_desc(addr);
133
134 return 0;
135}
[41d33ac]136
137/** Acquire console back for kernel
138 *
139 */
140void arch_grab_console(void)
141{
142 i8042_grab();
143}
144/** Return console to userspace
145 *
146 */
147void arch_release_console(void)
148{
149 i8042_release();
150}
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