source: mainline/arch/ia32/src/fpu_context.c@ c7bb8b05

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c7bb8b05 was 76cec1e, checked in by Jakub Jermar <jakub@…>, 20 years ago

Huge indentation fix.

  • Property mode set to 100644
File size: 2.1 KB
RevLine 
[0ca6faa]1/*
[54ca3523]2 * Copyright (C) 2005 Jakub Vana
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
[0ca6faa]29
30#include <fpu_context.h>
[79f1f38f]31#include <arch.h>
32#include <cpu.h>
33
[9c926f3]34void fpu_context_save(fpu_context_t *fctx)
[0ca6faa]35{
36}
37
38
[9c926f3]39void fpu_context_restore(fpu_context_t *fctx)
[0ca6faa]40{
[ea3fb2e]41 if(THREAD==CPU->fpu_owner) {reset_TS_flag(); }
[87be9cfb]42 else
43 {
44 set_TS_flag();
45 if((CPU->fpu_owner)!=NULL)(CPU->fpu_owner)->fpu_context_engaged=1;
46 }
[0ca6faa]47}
48
49
[9c926f3]50void fpu_lazy_context_save(fpu_context_t *fctx)
[0ca6faa]51{
[af22f158]52 asm
53 (
54 "push %%eax;"
55 "mov 0x8(%%esp),%%eax;"
56 "fnsave (%%eax);"
57 "pop %%eax;"
58 :"=m"(fctx)
59 :
60 :"eax"
61 );
[0ca6faa]62}
63
[9c926f3]64void fpu_lazy_context_restore(fpu_context_t *fctx)
[0ca6faa]65{
[af22f158]66 asm
67 (
68 "push %%eax;"
69 "mov 0x8(%%esp),%%eax;"
70 "frstor (%%eax);"
71 "pop %%eax;"
72 :"=m"(fctx)
73 :
74 :"eax"
75 );
[6a27d63]76}
77
78void fpu_init(void)
79{
[54ca3523]80 asm(
[76cec1e]81 "fninit;"
[54ca3523]82 );
[0ca6faa]83}
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