source: mainline/arch/ia32/src/fpu_context.c@ 73e9b49

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 73e9b49 was 3b05862f, checked in by Jakub Vana <jakub.vana@…>, 19 years ago

ia32 MMX and SSEx support

  • Property mode set to 100644
File size: 2.6 KB
RevLine 
[0ca6faa]1/*
[54ca3523]2 * Copyright (C) 2005 Jakub Vana
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
[0ca6faa]29
30#include <fpu_context.h>
[79f1f38f]31#include <arch.h>
32#include <cpu.h>
33
[3b05862f]34typedef void (*fpu_context_function)(fpu_context_t *fctx);
35
36static fpu_context_function fpu_save,fpu_restore;
37
38
39
40static void fpu_context_f_save(fpu_context_t *fctx)
[0ca6faa]41{
[005384ad]42 __asm__ volatile (
[e515167d]43 "fnsave %0"
[005384ad]44 : "=m"(*fctx)
[e515167d]45 );
[0ca6faa]46}
47
[3b05862f]48static void fpu_context_f_restore(fpu_context_t *fctx)
[0ca6faa]49{
[005384ad]50 __asm__ volatile (
[e515167d]51 "frstor %0"
[005384ad]52 : "=m"(*fctx)
[e515167d]53 );
[6a27d63]54}
55
[3b05862f]56static void fpu_context_fx_save(fpu_context_t *fctx)
57{
58 __asm__ volatile (
59 "fxsave %0"
60 : "=m"(*fctx)
61 );
62}
63
64static void fpu_context_fx_restore(fpu_context_t *fctx)
65{
66 __asm__ volatile (
67 "fxrstor %0"
68 : "=m"(*fctx)
69 );
70}
71
72/*
73 Setup using fxsr instruction
74*/
75void fpu_fxsr(void)
76{
77 fpu_save=fpu_context_fx_save;
78 fpu_restore=fpu_context_fx_restore;
79}
80/*
81 Setup using not fxsr instruction
82*/
83void fpu_fsr(void)
84{
85 fpu_save=fpu_context_f_save;
86 fpu_restore=fpu_context_f_restore;
87}
88
89
90
91void fpu_context_save(fpu_context_t *fctx)
92{
93 fpu_save(fctx);
94}
95
96void fpu_context_restore(fpu_context_t *fctx)
97{
98 fpu_restore(fctx);
99}
100
101
102
[f76fed4]103void fpu_init()
[6a27d63]104{
[3b05862f]105 __u32 help0=0,help1=0;
[005384ad]106 __asm__ volatile (
[3b05862f]107 "fninit;\n"
108 "stmxcsr %0\n"
109 "mov %0,%1;\n"
110 "or %2,%1;\n"
111 "mov %1,%0;\n"
112 "ldmxcsr %0;\n"
113 :"+m"(help0),"+r"(help1)
114 :"i"(0x1f80)
[54ca3523]115 );
[0ca6faa]116}
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