source: mainline/arch/ia32/src/fpu_context.c@ 005384ad

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 005384ad was 005384ad, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Fixed some stupid typos.

  • Property mode set to 100644
File size: 2.0 KB
RevLine 
[0ca6faa]1/*
[54ca3523]2 * Copyright (C) 2005 Jakub Vana
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
[0ca6faa]29
30#include <fpu_context.h>
[79f1f38f]31#include <arch.h>
32#include <cpu.h>
33
[9c926f3]34void fpu_context_save(fpu_context_t *fctx)
[0ca6faa]35{
36}
37
38
[9c926f3]39void fpu_context_restore(fpu_context_t *fctx)
[0ca6faa]40{
[005384ad]41 if (THREAD==CPU->fpu_owner)
42 reset_TS_flag();
43 else {
[87be9cfb]44 set_TS_flag();
[005384ad]45 if (CPU->fpu_owner != NULL)
46 (CPU->fpu_owner)->fpu_context_engaged=1;
[87be9cfb]47 }
[0ca6faa]48}
49
50
[9c926f3]51void fpu_lazy_context_save(fpu_context_t *fctx)
[0ca6faa]52{
[005384ad]53 __asm__ volatile (
[e515167d]54 "fnsave %0"
[005384ad]55 : "=m"(*fctx)
[e515167d]56 );
[005384ad]57 return;
[0ca6faa]58}
59
[9c926f3]60void fpu_lazy_context_restore(fpu_context_t *fctx)
[0ca6faa]61{
[005384ad]62 __asm__ volatile (
[e515167d]63 "frstor %0"
[005384ad]64 : "=m"(*fctx)
[e515167d]65 );
[005384ad]66 return;
[6a27d63]67}
68
69void fpu_init(void)
70{
[005384ad]71 __asm__ volatile (
[76cec1e]72 "fninit;"
[54ca3523]73 );
[0ca6faa]74}
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