source: mainline/arch/ia32/src/cpu/cpu.c@ 5f0c664

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5f0c664 was 39cea6a, checked in by Jakub Jermar <jakub@…>, 19 years ago

Cleanup pm.c and pm.h code on ia32 and amd64.
Add before_task_runs() and before_task_runs_arch() for each architecture.
Add ia32 and amd64 code to ensure I/O Permission Bitmap update.

  • Property mode set to 100644
File size: 3.7 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/cpu.h>
30#include <arch/cpuid.h>
31#include <arch/pm.h>
32
33#include <arch.h>
34#include <arch/types.h>
35#include <print.h>
36#include <typedefs.h>
37#include <fpu_context.h>
38
39#include <arch/smp/apic.h>
40
41/*
42 * Identification of CPUs.
43 * Contains only non-MP-Specification specific SMP code.
44 */
45#define AMD_CPUID_EBX 0x68747541
46#define AMD_CPUID_ECX 0x444d4163
47#define AMD_CPUID_EDX 0x69746e65
48
49#define INTEL_CPUID_EBX 0x756e6547
50#define INTEL_CPUID_ECX 0x6c65746e
51#define INTEL_CPUID_EDX 0x49656e69
52
53
54enum vendor {
55 VendorUnknown=0,
56 VendorAMD,
57 VendorIntel
58};
59
60static char *vendor_str[] = {
61 "Unknown Vendor",
62 "AuthenticAMD",
63 "GenuineIntel"
64};
65
66void fpu_disable(void)
67{
68 __asm__ volatile (
69 "mov %%cr0,%%eax;"
70 "or $8,%%eax;"
71 "mov %%eax,%%cr0;"
72 :
73 :
74 :"%eax"
75 );
76}
77
78void fpu_enable(void)
79{
80 __asm__ volatile (
81 "mov %%cr0,%%eax;"
82 "and $0xffFFffF7,%%eax;"
83 "mov %%eax,%%cr0;"
84 :
85 :
86 :"%eax"
87 );
88}
89
90void cpu_arch_init(void)
91{
92 cpuid_feature_info fi;
93 cpuid_extended_feature_info efi;
94 cpu_info_t info;
95 __u32 help = 0;
96
97 CPU->arch.tss = tss_p;
98 CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
99
100 CPU->fpu_owner = NULL;
101
102 cpuid(1, &info);
103
104 fi.word = info.cpuid_edx;
105 efi.word = info.cpuid_ecx;
106
107 if (fi.bits.fxsr)
108 fpu_fxsr();
109 else
110 fpu_fsr();
111
112 if (fi.bits.sse) {
113 asm volatile (
114 "mov %%cr4,%0\n"
115 "or %1,%0\n"
116 "mov %0,%%cr4\n"
117 : "+r" (help)
118 : "i" (CR4_OSFXSR_MASK|(1<<10))
119 );
120 }
121}
122
123void cpu_identify(void)
124{
125 cpu_info_t info;
126
127 CPU->arch.vendor = VendorUnknown;
128 if (has_cpuid()) {
129 cpuid(0, &info);
130
131 /*
132 * Check for AMD processor.
133 */
134 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
135 CPU->arch.vendor = VendorAMD;
136 }
137
138 /*
139 * Check for Intel processor.
140 */
141 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
142 CPU->arch.vendor = VendorIntel;
143 }
144
145 cpuid(1, &info);
146 CPU->arch.family = (info.cpuid_eax>>8)&0xf;
147 CPU->arch.model = (info.cpuid_eax>>4)&0xf;
148 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
149 }
150}
151
152void cpu_print_report(cpu_t* m)
153{
154 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
155 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
156 m->frequency_mhz);
157}
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