source: mainline/arch/ia32/src/cpu/cpu.c@ 4b2c872d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4b2c872d was 1084a784, checked in by Jakub Jermar <jakub@…>, 20 years ago

mips32 memory management work.
TLB Refill Exception implemented (passed basic testing).
Remove bit g from struct entry_hi.
Add generic find_mapping().
Add asid to vm_t type, define asid_t to hide architecture specific differences.
Implement ASID allocation for mips32, dummy for other architectures.
Add THE→vm (a.k.a. VM).
Add vm_install_arch().
Move pte_t definition to arch/types.h on each architecture.
Fix PTL manipulating functions on mips32 to shift pfn by 12 instead of by 14.
Fix tlb_init_arch() to initialize all entries.

Other.
Remove unnecessary header files from arch.h
Add missing headers here and there.
Remove two unnecessary ld flags from mips32 makefile.

  • Property mode set to 100644
File size: 3.3 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/cpu.h>
30#include <arch/cpuid.h>
31#include <arch/pm.h>
32
33#include <arch.h>
34#include <arch/types.h>
35#include <print.h>
36#include <typedefs.h>
37#include <fpu_context.h>
38
39#include <arch/smp/apic.h>
40
41/*
42 * Identification of CPUs.
43 * Contains only non-MP-Specification specific SMP code.
44 */
45#define AMD_CPUID_EBX 0x68747541
46#define AMD_CPUID_ECX 0x444d4163
47#define AMD_CPUID_EDX 0x69746e65
48
49#define INTEL_CPUID_EBX 0x756e6547
50#define INTEL_CPUID_ECX 0x6c65746e
51#define INTEL_CPUID_EDX 0x49656e69
52
53
54enum vendor {
55 VendorUnknown=0,
56 VendorAMD,
57 VendorIntel
58};
59
60static char *vendor_str[] = {
61 "Unknown Vendor",
62 "AuthenticAMD",
63 "GenuineIntel"
64};
65
66void fpu_disable(void)
67{
68 __asm__ volatile (
69 "mov %%cr0,%%eax;"
70 "or $8,%%eax;"
71 "mov %%eax,%%cr0;"
72 :
73 :
74 :"%eax"
75 );
76}
77
78void fpu_enable(void)
79{
80 __asm__ volatile (
81 "mov %%cr0,%%eax;"
82 "and $0xffFFffF7,%%eax;"
83 "mov %%eax,%%cr0;"
84 :
85 :
86 :"%eax"
87 );
88}
89
90
91
92
93void cpu_arch_init(void)
94{
95 CPU->arch.tss = tss_p;
96 CPU->fpu_owner=NULL;
97}
98
99
100void cpu_identify(void)
101{
102 cpu_info_t info;
103 int i;
104
105 CPU->arch.vendor = VendorUnknown;
106 if (has_cpuid()) {
107 cpuid(0, &info);
108
109 /*
110 * Check for AMD processor.
111 */
112 if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
113 CPU->arch.vendor = VendorAMD;
114 }
115
116 /*
117 * Check for Intel processor.
118 */
119 if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
120 CPU->arch.vendor = VendorIntel;
121 }
122
123 cpuid(1, &info);
124 CPU->arch.family = (info.cpuid_eax>>8)&0xf;
125 CPU->arch.model = (info.cpuid_eax>>4)&0xf;
126 CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
127 }
128}
129
130void cpu_print_report(cpu_t* m)
131{
132 printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
133 m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
134 m->frequency_mhz);
135}
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