source: mainline/arch/ia32/include/smp/apic.h@ 457d18a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 457d18a was 93e90c7, checked in by Jakub Jermar <jakub@…>, 20 years ago

ia32 work.
Initialize LDR and DFR registers in Local APIC so that logical destination addresses work.
  • Property mode set to 100644
File size: 9.6 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __APIC_H__
30#define __APIC_H__
31
32#include <arch/types.h>
33#include <cpu.h>
34
35#define FIXED (0<<0)
36#define LOPRI (1<<0)
37
38#define APIC_ID_COUNT 16
39
40/* local APIC macros */
41#define IPI_INIT 0
42#define IPI_STARTUP 0
43
44/** Delivery modes. */
45#define DELMOD_FIXED 0x0
46#define DELMOD_LOWPRI 0x1
47#define DELMOD_SMI 0x2
48/* 0x3 reserved */
49#define DELMOD_NMI 0x4
50#define DELMOD_INIT 0x5
51#define DELMOD_STARTUP 0x6
52#define DELMOD_EXTINT 0x7
53
54/** Destination modes. */
55#define DESTMOD_PHYS 0x0
56#define DESTMOD_LOGIC 0x1
57
58/** Trigger Modes. */
59#define TRIGMOD_EDGE 0x0
60#define TRIGMOD_LEVEL 0x1
61
62/** Levels. */
63#define LEVEL_DEASSERT 0x0
64#define LEVEL_ASSERT 0x1
65
66/** Destination Shorthands. */
67#define SHORTHAND_NONE 0x0
68#define SHORTHAND_SELF 0x1
69#define SHORTHAND_ALL_INCL 0x2
70#define SHORTHAND_ALL_EXCL 0x3
71
72/** Interrupt Input Pin Polarities. */
73#define POLARITY_HIGH 0x0
74#define POLARITY_LOW 0x1
75
76/** Divide Values. (Bit 2 is always 0) */
77#define DIVIDE_2 0x0
78#define DIVIDE_4 0x1
79#define DIVIDE_8 0x2
80#define DIVIDE_16 0x3
81#define DIVIDE_32 0x8
82#define DIVIDE_64 0x9
83#define DIVIDE_128 0xa
84#define DIVIDE_1 0xb
85
86/** Timer Modes. */
87#define TIMER_ONESHOT 0x0
88#define TIMER_PERIODIC 0x1
89
90/** Delivery status. */
91#define DELIVS_IDLE 0x0
92#define DELIVS_PENDING 0x1
93
94/** Destination masks. */
95#define DEST_ALL 0xff
96
97/** Dest format models. */
98#define MODEL_FLAT 0xf
99#define MODEL_CLUSTER 0x0
100
101/** Interrupt Command Register. */
102#define ICRlo (0x300/sizeof(__u32))
103#define ICRhi (0x310/sizeof(__u32))
104struct icr {
105 union {
106 __u32 lo;
107 struct {
108 __u8 vector; /**< Interrupt Vector. */
109 unsigned delmod : 3; /**< Delivery Mode. */
110 unsigned destmod : 1; /**< Destination Mode. */
111 unsigned delivs : 1; /**< Delivery status (RO). */
112 unsigned : 1; /**< Reserved. */
113 unsigned level : 1; /**< Level. */
114 unsigned trigger_mode : 1; /**< Trigger Mode. */
115 unsigned : 2; /**< Reserved. */
116 unsigned shorthand : 2; /**< Destination Shorthand. */
117 unsigned : 12; /**< Reserved. */
118 } __attribute__ ((packed));
119 };
120 union {
121 __u32 hi;
122 struct {
123 unsigned : 24; /**< Reserved. */
124 __u8 dest; /**< Destination field. */
125 } __attribute__ ((packed));
126 };
127} __attribute__ ((packed));
128typedef struct icr icr_t;
129
130/* End Of Interrupt */
131#define EOI (0x0b0/sizeof(__u32))
132
133/** Error Status Register. */
134#define ESR (0x280/sizeof(__u32))
135union esr {
136 __u32 value;
137 __u8 err_bitmap;
138 struct {
139 unsigned send_checksum_error : 1;
140 unsigned receive_checksum_error : 1;
141 unsigned send_accept_error : 1;
142 unsigned receive_accept_error : 1;
143 unsigned : 1;
144 unsigned send_illegal_vector : 1;
145 unsigned received_illegal_vector : 1;
146 unsigned illegal_register_address : 1;
147 unsigned : 24;
148 } __attribute__ ((packed));
149};
150typedef union esr esr_t;
151
152/* Task Priority Register */
153#define TPR (0x080/sizeof(__u32))
154#define TPRClear 0xffffff00
155
156/** Spurious-Interrupt Vector Register. */
157#define SVR (0x0f0/sizeof(__u32))
158union svr {
159 __u32 value;
160 struct {
161 __u8 vector; /**< Spurious Vector */
162 unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable */
163 unsigned focus_checking : 1; /**< Focus Processor Checking */
164 unsigned : 22; /**< Reserved. */
165 } __attribute__ ((packed));
166};
167typedef union svr svr_t;
168
169/** Time Divide Configuration Register. */
170#define TDCR (0x3e0/sizeof(__u32))
171union tdcr {
172 __u32 value;
173 struct {
174 unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */
175 unsigned : 28; /**< Reserved. */
176 } __attribute__ ((packed));
177};
178typedef union tdcr tdcr_t;
179
180/* Initial Count Register for Timer */
181#define ICRT (0x380/sizeof(__u32))
182
183/* Current Count Register for Timer */
184#define CCRT (0x390/sizeof(__u32))
185
186/** LVT Timer register. */
187#define LVT_Tm (0x320/sizeof(__u32))
188union lvt_tm {
189 __u32 value;
190 struct {
191 __u8 vector; /**< Local Timer Interrupt vector. */
192 unsigned : 4; /**< Reserved. */
193 unsigned delivs : 1; /**< Delivery status (RO). */
194 unsigned : 3; /**< Reserved. */
195 unsigned masked : 1; /**< Interrupt Mask. */
196 unsigned mode : 1; /**< Timer Mode. */
197 unsigned : 14; /**< Reserved. */
198 } __attribute__ ((packed));
199};
200typedef union lvt_tm lvt_tm_t;
201
202/** LVT LINT registers. */
203#define LVT_LINT0 (0x350/sizeof(__u32))
204#define LVT_LINT1 (0x360/sizeof(__u32))
205union lvt_lint {
206 __u32 value;
207 struct {
208 __u8 vector; /**< LINT Interrupt vector. */
209 unsigned delmod : 3; /**< Delivery Mode. */
210 unsigned : 1; /**< Reserved. */
211 unsigned delivs : 1; /**< Delivery status (RO). */
212 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
213 unsigned irr : 1; /**< Remote IRR (RO). */
214 unsigned trigger_mode : 1; /**< Trigger Mode. */
215 unsigned masked : 1; /**< Interrupt Mask. */
216 unsigned : 15; /**< Reserved. */
217 } __attribute__ ((packed));
218};
219typedef union lvt_lint lvt_lint_t;
220
221/** LVT Error register. */
222#define LVT_Err (0x370/sizeof(__u32))
223union lvt_error {
224 __u32 value;
225 struct {
226 __u8 vector; /**< Local Timer Interrupt vector. */
227 unsigned : 4; /**< Reserved. */
228 unsigned delivs : 1; /**< Delivery status (RO). */
229 unsigned : 3; /**< Reserved. */
230 unsigned masked : 1; /**< Interrupt Mask. */
231 unsigned : 15; /**< Reserved. */
232 } __attribute__ ((packed));
233};
234typedef union lvt_error lvt_error_t;
235
236/** Local APIC ID Register. */
237#define L_APIC_ID (0x020/sizeof(__u32))
238union l_apic_id {
239 __u32 value;
240 struct {
241 unsigned : 24; /**< Reserved. */
242 __u8 apic_id; /**< Local APIC ID. */
243 } __attribute__ ((packed));
244};
245typedef union l_apic_id l_apic_id_t;
246
247/* Local APIC Version Register */
248#define LAVR (0x030/sizeof(__u32))
249#define LAVR_Mask 0xff
250#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)
251#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))
252#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)
253
254/** Logical Destination Register. */
255#define LDR (0x0d0/sizeof(__u32))
256union ldr {
257 __u32 value;
258 struct {
259 unsigned : 24; /**< Reserver. */
260 __u8 id; /**< Logical APIC ID. */
261 } __attribute__ ((packed));
262};
263typedef union ldr ldr_t;
264
265/** Destination Format Register. */
266#define DFR (0x0e0/sizeof(__u32))
267union dfr {
268 __u32 value;
269 struct {
270 unsigned : 28; /**< Reserved, all ones. */
271 unsigned model : 4; /**< Model. */
272 } __attribute__ ((packed));
273};
274typedef union dfr dfr_t;
275
276/* IO APIC */
277#define IOREGSEL (0x00/sizeof(__u32))
278#define IOWIN (0x10/sizeof(__u32))
279
280#define IOAPICID 0x00
281#define IOAPICVER 0x01
282#define IOAPICARB 0x02
283#define IOREDTBL 0x10
284
285/** I/O Register Select Register. */
286union io_regsel {
287 __u32 value;
288 struct {
289 __u8 reg_addr; /**< APIC Register Address. */
290 unsigned : 24; /**< Reserved. */
291 } __attribute__ ((packed));
292};
293typedef union io_regsel io_regsel_t;
294
295/** I/O Redirection Register. */
296struct io_redirection_reg {
297 union {
298 __u32 lo;
299 struct {
300 __u8 intvec; /**< Interrupt Vector. */
301 unsigned delmod : 3; /**< Delivery Mode. */
302 unsigned destmod : 1; /**< Destination mode. */
303 unsigned delivs : 1; /**< Delivery status (RO). */
304 unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
305 unsigned irr : 1; /**< Remote IRR (RO). */
306 unsigned trigger_mode : 1; /**< Trigger Mode. */
307 unsigned masked : 1; /**< Interrupt Mask. */
308 unsigned : 15; /**< Reserved. */
309 } __attribute__ ((packed));
310 };
311 union {
312 __u32 hi;
313 struct {
314 unsigned : 24; /**< Reserved. */
315 __u8 dest : 8; /**< Destination Field. */
316 } __attribute__ ((packed));
317 };
318
319} __attribute__ ((packed));
320typedef struct io_redirection_reg io_redirection_reg_t;
321
322
323/** IO APIC Identification Register. */
324union io_apic_id {
325 __u32 value;
326 struct {
327 unsigned : 24; /**< Reserved. */
328 unsigned apic_id : 4; /**< IO APIC ID. */
329 unsigned : 4; /**< Reserved. */
330 } __attribute__ ((packed));
331};
332typedef union io_apic_id io_apic_id_t;
333
334extern volatile __u32 *l_apic;
335extern volatile __u32 *io_apic;
336
337extern __u32 apic_id_mask;
338
339extern void apic_init(void);
340
341extern void l_apic_init(void);
342extern void l_apic_eoi(void);
343extern int l_apic_broadcast_custom_ipi(__u8 vector);
344extern int l_apic_send_init_ipi(__u8 apicid);
345extern void l_apic_debug(void);
346extern __u8 l_apic_id(void);
347
348extern __u32 io_apic_read(__u8 address);
349extern void io_apic_write(__u8 address , __u32 x);
350extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
351extern void io_apic_disable_irqs(__u16 irqmask);
352extern void io_apic_enable_irqs(__u16 irqmask);
353
354#endif
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