source: mainline/arch/ia32/include/mm/page.h@ 607c5f9

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 607c5f9 was 1084a784, checked in by Jakub Jermar <jakub@…>, 20 years ago

mips32 memory management work.
TLB Refill Exception implemented (passed basic testing).
Remove bit g from struct entry_hi.
Add generic find_mapping().
Add asid to vm_t type, define asid_t to hide architecture specific differences.
Implement ASID allocation for mips32, dummy for other architectures.
Add THE→vm (a.k.a. VM).
Add vm_install_arch().
Move pte_t definition to arch/types.h on each architecture.
Fix PTL manipulating functions on mips32 to shift pfn by 12 instead of by 14.
Fix tlb_init_arch() to initialize all entries.

Other.
Remove unnecessary header files from arch.h
Add missing headers here and there.
Remove two unnecessary ld flags from mips32 makefile.

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ia32_PAGE_H__
30#define __ia32_PAGE_H__
31
32#define PAGE_SIZE FRAME_SIZE
33
34#ifndef __ASM__
35# define KA2PA(x) (((__address) (x)) - 0x80000000)
36# define PA2KA(x) (((__address) (x)) + 0x80000000)
37#else
38# define KA2PA(x) ((x) - 0x80000000)
39# define PA2KA(x) ((x) + 0x80000000)
40#endif
41
42/*
43 * Implementation of generic 4-level page table interface.
44 * IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
45 */
46#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>22)&0x3ff)
47#define PTL1_INDEX_ARCH(vaddr) 0
48#define PTL2_INDEX_ARCH(vaddr) 0
49#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x3ff)
50
51#define GET_PTL0_ADDRESS_ARCH() ((pte_t *) read_cr3())
52#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address)<<12))
53#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
54#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
55#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((__address)((((pte_t *)(ptl3))[(i)].frame_address)<<12))
56
57#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((__address) (ptl0)))
58#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].frame_address = (a)>>12)
59#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
60#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
61#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].frame_address = (a)>>12)
62
63#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
64#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
65#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
66#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
67
68#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
69#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
70#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
71#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
72
73#ifndef __ASM__
74
75#include <mm/page.h>
76#include <arch/types.h>
77#include <arch/mm/frame.h>
78#include <typedefs.h>
79
80struct page_specifier {
81 unsigned present : 1;
82 unsigned writeable : 1;
83 unsigned uaccessible : 1;
84 unsigned page_write_through : 1;
85 unsigned page_cache_disable : 1;
86 unsigned accessed : 1;
87 unsigned dirty : 1;
88 unsigned : 2;
89 unsigned avl : 3;
90 unsigned frame_address : 20;
91} __attribute__ ((packed));
92
93static inline int get_pt_flags(pte_t *pt, index_t i)
94{
95 pte_t *p = &pt[i];
96
97 return (
98 (!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
99 (!p->present)<<PAGE_PRESENT_SHIFT |
100 p->uaccessible<<PAGE_USER_SHIFT |
101 1<<PAGE_READ_SHIFT |
102 p->writeable<<PAGE_WRITE_SHIFT |
103 1<<PAGE_EXEC_SHIFT
104 );
105}
106
107static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
108{
109 pte_t *p = &pt[i];
110
111 p->page_cache_disable = !(flags & PAGE_CACHEABLE);
112 p->present = !(flags & PAGE_NOT_PRESENT);
113 p->uaccessible = (flags & PAGE_USER) != 0;
114 p->writeable = (flags & PAGE_WRITE) != 0;
115}
116
117extern void page_arch_init(void);
118
119#endif /* __ASM__ */
120
121#endif
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