source: mainline/arch/ia32/include/atomic.h@ 73a4bab

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 73a4bab was 73a4bab, checked in by Jakub Vana <jakub.vana@…>, 20 years ago

Atomic inc & dec functions synchronized on all ia32,ia64 and mips platforms. Now there are 3 versions which returns no value, new value and old value och changed variable.

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ia32_ATOMIC_H__
30#define __ia32_ATOMIC_H__
31
32#include <arch/types.h>
33
34typedef volatile __u32 atomic_t;
35
36static inline void atomic_inc(atomic_t *val) {
37#ifdef CONFIG_SMP
38 __asm__ volatile ("lock incl %0\n" : "+m" (*val));
39#else
40 __asm__ volatile ("incl %0\n" : "+m" (*val));
41#endif /* CONFIG_SMP */
42}
43
44static inline void atomic_dec(atomic_t *val) {
45#ifdef CONFIG_SMP
46 __asm__ volatile ("lock decl %0\n" : "+m" (*val));
47#else
48 __asm__ volatile ("decl %0\n" : "+m" (*val));
49#endif /* CONFIG_SMP */
50}
51
52static inline atomic_t atomic_inc_pre(atomic_t *val)
53{
54 atomic_t r;
55 __asm__ volatile (
56 "movl $1,%0;"
57 "lock xaddl %0,%1;"
58 : "=r"(r), "+m" (*val)
59 );
60 return r;
61}
62
63
64
65static inline atomic_t atomic_dec_pre(atomic_t *val)
66{
67 atomic_t r;
68 __asm__ volatile (
69 "movl $-1,%0;"
70 "lock xaddl %0,%1;"
71 : "=r"(r), "+m" (*val)
72 );
73 return r;
74}
75
76#define atomic_inc_post(val) (atomic_inc_pre(val)+1)
77#define atomic_dec_post(val) (atomic_dec_pre(val)-1)
78
79
80
81static inline int test_and_set(volatile int *val) {
82 int v;
83
84 __asm__ volatile (
85 "movl $1, %0\n"
86 "xchgl %0, %1\n"
87 : "=r" (v),"+m" (*val)
88 );
89
90 return v;
91}
92
93
94extern void spinlock_arch(volatile int *val);
95
96#endif
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