[f761f1eb] | 1 | /*
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| 2 | * Copyright (C) 2001-2004 Jakub Jermar
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[397c77f] | 29 | #ifndef __ia32_ASM_H__
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| 30 | #define __ia32_ASM_H__
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[f761f1eb] | 31 |
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| 32 | #include <arch/types.h>
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| 33 | #include <typedefs.h>
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[b52da8d7] | 34 | #include <config.h>
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[f761f1eb] | 35 | #include <synch/spinlock.h>
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[5d721f0] | 36 | #include <arch/boot/memmap.h>
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[361635c] | 37 | #include <config.h>
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[f761f1eb] | 38 |
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| 39 | extern __u32 interrupt_handler_size;
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| 40 |
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| 41 | extern void paging_on(void);
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| 42 |
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| 43 | extern void interrupt_handlers(void);
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| 44 |
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| 45 | extern __u8 inb(int port);
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| 46 | extern __u16 inw(int port);
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| 47 | extern __u32 inl(int port);
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| 48 |
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| 49 | extern void outb(int port, __u8 b);
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| 50 | extern void outw(int port, __u16 w);
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| 51 | extern void outl(int port, __u32 l);
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| 52 |
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| 53 | extern void enable_l_apic_in_msr(void);
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| 54 |
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[18e0a6c] | 55 | /** Halt CPU
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| 56 | *
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| 57 | * Halt the current CPU until interrupt event.
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| 58 | */
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| 59 | static inline void cpu_halt(void) { __asm__("hlt"); };
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| 60 | static inline void cpu_sleep(void) { __asm__("hlt"); };
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[f761f1eb] | 61 |
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[18e0a6c] | 62 | /** Read CR2
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| 63 | *
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| 64 | * Return value in CR2
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| 65 | *
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| 66 | * @return Value read.
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| 67 | */
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| 68 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; }
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[0f4e706] | 69 |
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[18e0a6c] | 70 | /** Write CR3
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| 71 | *
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| 72 | * Write value to CR3.
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| 73 | *
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| 74 | * @param v Value to be written.
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| 75 | */
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| 76 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
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| 77 |
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| 78 | /** Read CR3
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| 79 | *
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| 80 | * Return value in CR3
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| 81 | *
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| 82 | * @return Value read.
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| 83 | */
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| 84 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; }
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| 85 |
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| 86 | /** Write DR0
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| 87 | *
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| 88 | * Write value to DR0.
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| 89 | *
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| 90 | * @param v Value to be written.
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| 91 | */
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| 92 | static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); }
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| 93 |
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| 94 | /** Read DR0
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| 95 | *
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| 96 | * Return value in DR0
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| 97 | *
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| 98 | * @return Value read.
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| 99 | */
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| 100 | static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; }
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| 101 |
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| 102 | /** Set priority level low
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| 103 | *
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| 104 | * Enable interrupts and return previous
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| 105 | * value of EFLAGS.
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| 106 | */
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| 107 | static inline pri_t cpu_priority_low(void) {
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| 108 | pri_t v;
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| 109 | __asm__ volatile (
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| 110 | "pushf\n"
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| 111 | "popl %0\n"
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| 112 | "sti\n"
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| 113 | : "=r" (v)
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| 114 | );
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| 115 | return v;
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| 116 | }
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| 117 |
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| 118 | /** Set priority level high
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| 119 | *
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| 120 | * Disable interrupts and return previous
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| 121 | * value of EFLAGS.
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| 122 | */
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| 123 | static inline pri_t cpu_priority_high(void) {
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| 124 | pri_t v;
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| 125 | __asm__ volatile (
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| 126 | "pushf\n"
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| 127 | "popl %0\n"
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| 128 | "cli\n"
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| 129 | : "=r" (v)
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| 130 | );
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| 131 | return v;
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| 132 | }
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| 133 |
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| 134 | /** Restore priority level
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| 135 | *
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| 136 | * Restore EFLAGS.
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| 137 | */
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| 138 | static inline void cpu_priority_restore(pri_t pri) {
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| 139 | __asm__ volatile (
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| 140 | "pushl %0\n"
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| 141 | "popf\n"
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| 142 | : : "r" (pri)
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| 143 | );
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| 144 | }
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| 145 |
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| 146 | /** Return raw priority level
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| 147 | *
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| 148 | * Return EFLAFS.
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| 149 | */
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| 150 | static inline pri_t cpu_priority_read(void) {
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| 151 | pri_t v;
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| 152 | __asm__ volatile (
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| 153 | "pushf\n"
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| 154 | "popl %0\n"
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| 155 | : "=r" (v)
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| 156 | );
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| 157 | return v;
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| 158 | }
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[c9b8c5c] | 159 |
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[361635c] | 160 | /** Return base address of current stack
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| 161 | *
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| 162 | * Return the base address of the current stack.
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| 163 | * The stack is assumed to be STACK_SIZE bytes long.
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[1fbbcd6] | 164 | * The stack must start on page boundary.
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[361635c] | 165 | */
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| 166 | static inline __address get_stack_base(void)
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| 167 | {
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| 168 | __address v;
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| 169 |
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| 170 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
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| 171 |
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| 172 | return v;
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| 173 | }
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| 174 |
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[f761f1eb] | 175 | #endif
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