source: mainline/arch/amd64/src/interrupt.c@ ab08b42

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ab08b42 was ab08b42, checked in by Ondrej Palkovsky <ondrap@…>, 20 years ago

Added symbol table lookup in exceptions.
This breaks ia64 & ppc architecture compiles.

  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*
2 * Copyright (C) 2001-2004 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <arch/interrupt.h>
30#include <print.h>
31#include <debug.h>
32#include <panic.h>
33#include <arch/i8259.h>
34#include <func.h>
35#include <cpu.h>
36#include <arch/asm.h>
37#include <mm/tlb.h>
38#include <arch.h>
39#include <symtab.h>
40
41#define PRINT_INFO_ERRCODE(x) { \
42 char *symbol = get_symtab_entry(stack[1]); \
43 if (!symbol) \
44 symbol = ""; \
45 printf("----------------EXCEPTION OCCURED----------------\n"); \
46 printf("%%rip: %Q (%s)\n",x[1],symbol); \
47 printf("ERROR_WORD=%Q\n", x[0]); \
48 printf("%%rcs=%Q,flags=%Q\n", x[2], x[3]); \
49 printf("%%rax=%Q, %%rbx=%Q, %%rcx=%Q\n",x[-1],x[-2],x[-3]); \
50 printf("%%rdx=%Q, %%rsi=%Q, %%rdi=%Q\n",x[-4],x[-5],x[-6]); \
51 printf("%%r8 =%Q, %%r9 =%Q, %%r10=%Q\n",x[-7],x[-8],x[-9]); \
52 printf("%%r11=%Q, %%r12=%Q, %%r13=%Q\n",x[-10],x[-11],x[-12]); \
53 printf("%%r14=%Q, %%r15=%Q, %%rsp=%Q\n",x[-13],x[-14],x); \
54 printf("stack: %Q, %Q, %Q\n", x[5], x[6], x[7]); \
55 printf(" %Q, %Q, %Q\n", x[8], x[9], x[10]); \
56 }
57
58/*
59 * Interrupt and exception dispatching.
60 */
61
62static iroutine ivt[IVT_ITEMS];
63
64void (* disable_irqs_function)(__u16 irqmask) = NULL;
65void (* enable_irqs_function)(__u16 irqmask) = NULL;
66void (* eoi_function)(void) = NULL;
67
68iroutine trap_register(__u8 n, iroutine f)
69{
70 ASSERT(n < IVT_ITEMS);
71
72 iroutine old;
73
74 old = ivt[n];
75 ivt[n] = f;
76
77 return old;
78}
79
80/*
81 * Called directly from the assembler code.
82 * CPU is cpu_priority_high().
83 */
84void trap_dispatcher(__u8 n, __native stack[])
85{
86 ASSERT(n < IVT_ITEMS);
87
88 ivt[n](n, stack);
89}
90
91void null_interrupt(__u8 n, __native stack[])
92{
93 printf("----------------EXCEPTION OCCURED----------------\n");
94 printf("int %d: null_interrupt\n", n);
95 printf("stack: %L, %L, %L, %L\n", stack[0], stack[1], stack[2], stack[3]);
96 panic("unserviced interrupt\n");
97}
98
99void gp_fault(__u8 n, __native stack[])
100{
101 PRINT_INFO_ERRCODE(stack);
102 panic("general protection fault\n");
103}
104
105void ss_fault(__u8 n, __native stack[])
106{
107 PRINT_INFO_ERRCODE(stack);
108 panic("stack fault\n");
109}
110
111
112void nm_fault(__u8 n, __native stack[])
113{
114 reset_TS_flag();
115 if ((CPU->fpu_owner)!=NULL) {
116 fpu_lazy_context_save(&((CPU->fpu_owner)->saved_fpu_context));
117 (CPU->fpu_owner)->fpu_context_engaged=0; /* don't prevent migration */
118 }
119 if(THREAD->fpu_context_exists) fpu_lazy_context_restore(&(THREAD->saved_fpu_context));
120 else {fpu_init();THREAD->fpu_context_exists=1;}
121 CPU->fpu_owner=THREAD;
122}
123
124
125
126void page_fault(__u8 n, __native stack[])
127{
128 PRINT_INFO_ERRCODE(stack);
129 printf("Page fault address: %Q\n", read_cr2());
130 panic("page fault\n");
131}
132
133void syscall(__u8 n, __native stack[])
134{
135 printf("cpu%d: syscall\n", CPU->id);
136 thread_usleep(1000);
137}
138
139void tlb_shootdown_ipi(__u8 n, __native stack[])
140{
141 trap_virtual_eoi();
142 tlb_shootdown_ipi_recv();
143}
144
145void wakeup_ipi(__u8 n, __native stack[])
146{
147 trap_virtual_eoi();
148}
149
150void trap_virtual_enable_irqs(__u16 irqmask)
151{
152 if (enable_irqs_function)
153 enable_irqs_function(irqmask);
154 else
155 panic("no enable_irqs_function\n");
156}
157
158void trap_virtual_disable_irqs(__u16 irqmask)
159{
160 if (disable_irqs_function)
161 disable_irqs_function(irqmask);
162 else
163 panic("no disable_irqs_function\n");
164}
165
166void trap_virtual_eoi(void)
167{
168 if (eoi_function)
169 eoi_function();
170 else
171 panic("no eoi_function\n");
172
173}
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